Changed a lot of code to the new RTLIL::Wire constructors

2 files changed, 8 insertions, 22 deletions

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 4d9a6c136..41cfe88f6 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -313,11 +313,9 @@ static void handle_loops()
 				continue;
 			}
 
-			RTLIL::Wire *wire = new RTLIL::Wire;
 			std::stringstream sstr;
 			sstr << "$abcloop$" << (RTLIL::autoidx++);
-			wire->name = sstr.str();
-			module->wires[wire->name] = wire;
+			RTLIL::Wire *wire = module->addWire(sstr.str());
 
 			bool first_line = true;
 			for (int id2 : edges[id1]) {
@@ -691,9 +689,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 			log_error("ABC output file does not contain a module `netlist'.\n");
 		for (auto &it : mapped_mod->wires) {
 			RTLIL::Wire *w = it.second;
-			RTLIL::Wire *wire = new RTLIL::Wire;
-			wire->name = remap_name(w->name);
-			module->wires[wire->name] = wire;
+			RTLIL::Wire *wire = module->addWire(remap_name(w->name));
 			design->select(module, wire);
 		}
 
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 45a9ac765..e86afa1b7 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -98,14 +98,12 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 			if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
 				char *p;
 				while ((p = strtok(NULL, " \t\r\n")) != NULL) {
-					RTLIL::Wire *wire = new RTLIL::Wire;
-					wire->name = stringf("\\%s", p);
+					RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
 					wire->port_id = ++port_count;
 					if (!strcmp(cmd, ".inputs"))
 						wire->port_input = true;
 					else
 						wire->port_output = true;
-					module->add(wire);
 				}
 				continue;
 			}
@@ -115,17 +113,11 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				char *d = strtok(NULL, " \t\r\n");
 				char *q = strtok(NULL, " \t\r\n");
 
-				if (module->wires.count(RTLIL::escape_id(d)) == 0) {
-					RTLIL::Wire *wire = new RTLIL::Wire;
-					wire->name = RTLIL::escape_id(d);
-					module->add(wire);
-				}
+				if (module->wires.count(RTLIL::escape_id(d)) == 0)
+					module->addWire(RTLIL::escape_id(d));
 
-				if (module->wires.count(RTLIL::escape_id(q)) == 0) {
-					RTLIL::Wire *wire = new RTLIL::Wire;
-					wire->name = RTLIL::escape_id(q);
-					module->add(wire);
-				}
+				if (module->wires.count(RTLIL::escape_id(q)) == 0)
+					module->addWire(RTLIL::escape_id(q));
 
 				RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
 				cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
@@ -162,9 +154,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 					if (module->wires.count(stringf("\\%s", p)) > 0) {
 						wire = module->wires.at(stringf("\\%s", p));
 					} else {
-						wire = new RTLIL::Wire;
-						wire->name = stringf("\\%s", p);
-						module->add(wire);
+						wire = module->addWire(stringf("\\%s", p));
 					}
 					input_sig.append(wire);
 				}