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* Use in-tree include directory in manual buildXiretza2020-05-301-1/+4
* Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-292-1/+24
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| * Document division and modulo cellsXiretza2020-05-281-0/+23
| * Add flooring division operatorXiretza2020-05-281-1/+1
| * Add flooring modulo operatorXiretza2020-05-281-1/+1
* | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+6
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* Update CHANGELOG and manual for departure from upstreamEddie Hung2020-04-271-2/+3
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-198/+2300
* fix typo in `write_smt2` helpTeguh Hofstee2020-03-231-1/+1
* manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
* Merge pull request #1553 from whitequark/manual-dffxClaire Wolf2020-01-281-11/+90
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| * manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells.whitequark2019-12-051-11/+90
* | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-151-2/+2
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| * | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-2/+2
* | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
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| * | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
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* / manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-1/+1
* manual: explain the purpose of `sync always`.whitequark2019-07-021-2/+3
* Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
* Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-1/+1
* Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+4
* manual: document some gates.whitequark2019-01-141-9/+11
* manual: explain $tribuf cell.whitequark2019-01-141-0/+10
* Fix typo in manualClifford Wolf2019-01-071-1/+1
* manual: make description of $meminit ports match reality.whitequark2018-12-211-3/+15
* manual: fix typos.whitequark2018-12-201-2/+2
* manual: document $meminit cell and memory_* passes.whitequark2018-12-202-8/+23
* Update command reference manualClifford Wolf2018-10-161-140/+1200
* Fixed typo in "verilog_write" help messageacw12512018-09-181-2/+2
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-202-4/+4
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+2
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-1/+2
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+1
* Use -E sed parameter instead of -r.Piotr Esden-Tempski2017-02-041-1/+1
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+1
* Updated command reference in manualClifford Wolf2016-11-021-100/+568
* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+4
* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
* Removed $predict againClifford Wolf2016-08-281-1/+1
* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-1/+1
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-1/+1
* Added warning about adding fsm_encoding attributes to wires to manualClifford Wolf2016-07-081-0/+4
* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+4
* Minor presentation fixesClifford Wolf2016-05-141-1/+1
* Added "yosys -D" featureClifford Wolf2016-04-213-3/+3
* Fix a few typos in the manualWladimir J. van der Laan2016-04-031-3/+3
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