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author | acw1251 <acwright@mit.edu> | 2018-09-18 13:34:30 -0400 |
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committer | acw1251 <acwright@mit.edu> | 2018-09-18 13:34:30 -0400 |
commit | efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe (patch) | |
tree | e0d9302ac85ad4a3df2c960b650d6d94fa37e58b /manual | |
parent | 592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff) | |
download | yosys-efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe.tar.gz yosys-efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe.tar.bz2 yosys-efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe.zip |
Fixed typo in "verilog_write" help message
Diffstat (limited to 'manual')
-rw-r--r-- | manual/command-reference-manual.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 8af8ccdd0..fea2354e6 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -4421,13 +4421,13 @@ Write the current design to a Verilog file. -nodec 32-bit constant values are by default dumped as decimal numbers, - not bit pattern. This option decativates this feature and instead + not bit pattern. This option deactivates this feature and instead will write out all constants in binary. -nostr Parameters and attributes that are specified as strings in the original input will be output as strings by this back-end. This - decativates this feature and instead will write string constants + deactivates this feature and instead will write string constants as binary numbers. -defparam |