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author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
commit | d7763634b68a735443c61aa32918ee0cdd6e9250 (patch) | |
tree | d04a1d072d727d0776c42f68668785403cc92bf5 /manual | |
parent | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (diff) | |
download | yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.gz yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.bz2 yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.zip |
After reading the SV spec, using non-standard predict() instead of expect()
Diffstat (limited to 'manual')
-rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 759a5bb6a..b1e000aa2 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$expect}, and {\tt \$equiv} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, and {\tt \$equiv} cells. \end{fixme} \begin{fixme} |