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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
| commit | eb67a7532bf1d8195216257a2d6d301c03980591 (patch) | |
| tree | f9246e5ace86c1cc365b4f5111061d99fbcc9aeb /manual | |
| parent | 2521ed305e9d48929c9ede93b8cb0069739408f5 (diff) | |
| download | yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.gz yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.bz2 yosys-eb67a7532bf1d8195216257a2d6d301c03980591.zip | |
Add $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index c36e61b05..277e89328 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,8 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, +{\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells. \end{fixme} \begin{fixme} |