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* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-082-0/+22
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* Remove a few functions that, in fact, did not exist in the first place.Marcelina Kościelnicka2021-03-061-2/+0
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* Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
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* Fix double-free on unmatched logger error patternZachary Snow2021-02-231-3/+3
| | | | | | | When an expected logger error pattern is unmatched, the logger raises another (hidden) error. Because of the previous ordering of actions, `logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()` twice, causing a double-free.
* int -> boolRobert Baruch2021-02-231-2/+2
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* Adds is_wire to SigBit and SigChunkRobert Baruch2021-02-231-0/+3
| | | Useful for PYOSYS because Python can't easily check wire against NULL.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* kernel/yosys.h: undef CONST on WIN32umarcor2020-12-281-2/+3
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* kernel: undef Tcl macros interfering with cxxrtl.whitequark2020-12-221-0/+2
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* Merge pull request #2487 from whitequark/cxxrtl-outliningwhitequark2020-12-191-1/+1
|\ | | | | CXXRTL: implement zero-cost full coverage debug information through the magic✨ of outlining🪄🎀🧹
| * kernel: make IdString::isPublic() const.whitequark2020-12-121-1/+1
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* | timinginfo: Error instead of segfault on const signals.Marcelina Kościelnicka2020-12-151-2/+2
|/ | | | Reported by @Ravenslofty
* bugpoint: add -wires option.whitequark2020-12-071-1/+1
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* tcl -h message only if YOSYS_ENABLE_TCL defined.nitz2020-11-231-0/+2
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* Expose abc and data paths as globalsMiodrag Milanovic2020-11-062-14/+61
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* Add new helper structures to represent memories.Marcelina Kościelnicka2020-10-212-0/+514
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* add IdString::isPublic()N. Engelhardt2020-09-031-0/+2
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-263-10/+10
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-1/+5
| | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* Respect \A_SIGNED for $shiftXiretza2020-08-182-42/+22
| | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* async2sync: Support all FF types.Marcelina Kościelnicka2020-07-301-0/+46
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* ffinit: Fortify the code a bit.Marcelina Kościelnicka2020-07-281-24/+19
| | | | | This fixes handling of messy cases involving repeatedly setting and removing the same init bit.
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-242-4/+67
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* Add utility module for representing flip-flops.Marcelina Kościelnicka2020-07-231-0/+440
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* Add utility module for dealing with init attributes.Marcelina Kościelnicka2020-07-231-0/+146
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+1
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* celltypes: Fix EN port name for some FF types.Marcelina Kościelnicka2020-07-201-4/+4
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* satgen: Move importCell out of the header.Marcelina Kościelnicka2020-07-192-1165/+1189
| | | | | This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
* verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-161-0/+2
| | | | See #2271.
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-254-9/+14
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).whitequark2020-06-191-0/+8
| | | | | | | | | | [[maybe_unused]] is available since C++17, so this commit adds a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-192-4/+4
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| * Use (and ignore) the expression provided to log_debug in NDEBUG builds.whitequark2020-06-191-2/+1
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| * Use (and ignore) the expression provided to log_assert in NDEBUG builds.whitequark2020-06-192-3/+1
| | | | | | | | | | This avoids warnings in NDEBUG builds emitted when a variable is only used in log_assert, but is always defined.
* | Merge pull request #2135 from boqwxp/qbfsat-timeinfoclairexen2020-06-251-10/+8
|\ \ | | | | | | log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
| * | log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`.Alberto Gonzalez2020-06-211-4/+0
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| * | log, qbfsat: Include child process time in `PerformanceTimer::query()` and ↵Alberto Gonzalez2020-06-211-6/+8
| | | | | | | | | | | | report the time for each call to the QBF-SAT solver.
| * | qbfsat: Simplify solution format and replace `SigBit::str()` with ↵Alberto Gonzalez2020-06-211-8/+0
| | | | | | | | | | | | | | | | | | `log_signal()`. Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
| * | qbfsat: Use bit precise mapping for hole value wires and a more robust hole ↵Alberto Gonzalez2020-06-211-0/+8
| | | | | | | | | | | | spec for writing to and specializing from a solution file.
* | | Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-232-0/+213
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* | | Add new builtin FF typesMarcelina Kościelnicka2020-06-233-47/+267
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* | Merge pull request #2177 from boqwxp/dict-iterator-jumpwhitequark2020-06-212-0/+25
|\ \ | | | | | | hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
| * | dict: Remove guard for past-the-end iterators that might mask problems in ↵Alberto Gonzalez2020-06-191-2/+2
| | | | | | | | | | | | | | | | | | static analysis. Co-Authored-By: whitequark <whitequark@whitequark.org>
| * | hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and ↵Alberto Gonzalez2020-06-192-0/+25
| |/ | | | | | | `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
* / rtlil: Add `Design::select()` for selecting whole modules.Alberto Gonzalez2020-06-191-0/+7
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* Add missing [[noreturn]] to log_file_error()Xiretza2020-06-191-1/+1
| | | | | | | | | | | | | Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not YS_NORETURN, so it got lost in #2173, resulting in warnings in frontends/ast/simplify.cc: frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^ frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^
* Use C++11 [[noreturn]] attribute.whitequark2020-06-193-8/+5
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* Use C++11 final/override keywords.whitequark2020-06-186-33/+25
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* MSVC defines TRANSPARENT tooAnonymous Maarten2020-06-171-4/+4
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* kernel: guard include of signal.h more precisely.whitequark2020-06-131-1/+3
| | | | | | Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM does not have signals. (Arguably Yosys was broken even before, it was just broken silently.)
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