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| author | Robert Baruch <robert.c.baruch@gmail.com> | 2021-02-21 20:00:31 -0800 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:52:43 +0100 |
| commit | 4b31223e60f8854d50c1d1bbddca528fbf37d261 (patch) | |
| tree | 6b2fd0c867bacf53596f14750c6742d19a326053 /kernel | |
| parent | 7c50b89b244ed23d42f95c3d08efde40ec7ddd82 (diff) | |
| download | yosys-4b31223e60f8854d50c1d1bbddca528fbf37d261.tar.gz yosys-4b31223e60f8854d50c1d1bbddca528fbf37d261.tar.bz2 yosys-4b31223e60f8854d50c1d1bbddca528fbf37d261.zip | |
int -> bool
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a5f170085..6170ea55e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -735,7 +735,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk extract(int offset, int length) const; inline int size() const { return width; } - inline int is_wire() const { return wire != NULL; } + inline bool is_wire() const { return wire != NULL; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; @@ -761,7 +761,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigBit &sigbit) = default; RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; - inline int is_wire() const { return wire != NULL; } + inline bool is_wire() const { return wire != NULL; } bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; |