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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-12-14 18:14:42 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-12-15 00:51:16 +0100 |
| commit | de991977385330dfd628f15440e90a607842fbc4 (patch) | |
| tree | 9d42dedc5e3321ca2b8a304c723dbf85a9d7d006 /kernel | |
| parent | 5a881497e12a100438a51a2f0c1b133a8cc389ff (diff) | |
| download | yosys-de991977385330dfd628f15440e90a607842fbc4.tar.gz yosys-de991977385330dfd628f15440e90a607842fbc4.tar.bz2 yosys-de991977385330dfd628f15440e90a607842fbc4.zip | |
timinginfo: Error instead of segfault on const signals.
Reported by @Ravenslofty
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/timinginfo.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index d818e580b..eba3386d6 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -88,10 +88,10 @@ struct TimingInfo auto src = cell->getPort(ID::SRC); auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) - if (!c.wire->port_input) + if (!c.wire || !c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) - if (!c.wire->port_output) + if (!c.wire || !c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); |