| Commit message (Expand) | Author | Age | Files | Lines |
* | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 8 | -86/+90 |
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| * | substr() -> compare() | Eddie Hung | 2019-08-07 | 2 | -32/+32 |
| * | RTLIL::S{0,1} -> State::S{0,1} for headers | Eddie Hung | 2019-08-07 | 5 | -40/+40 |
| * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -6/+6 |
| * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 5 | -80/+96 |
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| * | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
| * | | Fix typos | Eddie Hung | 2019-08-06 | 2 | -4/+4 |
| * | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -3/+3 |
| * | | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 2 | -7/+11 |
| * | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
* | | | Automatically prune init attributes in verific front-end, fixes #1237 | Clifford Wolf | 2019-08-07 | 1 | -5/+14 |
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* | | Merge pull request #1213 from YosysHQ/eddie/wreduce_add | Clifford Wolf | 2019-08-07 | 1 | -0/+2 |
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| * | | Add SigSpec::extract_end() convenience function | Eddie Hung | 2019-08-06 | 1 | -0/+1 |
| * | | Restore original SigSpec::extract() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| * | | Merge remote-tracking branch 'origin/master' into eddie/wreduce_add | Eddie Hung | 2019-08-06 | 10 | -28/+184 |
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| * | | Add an SigSpec::at(offset, defval) convenience method | Eddie Hung | 2019-07-19 | 1 | -0/+1 |
| * | | SigSpec::extract to take negative lengths | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
* | | | Merge pull request #1253 from YosysHQ/clifford/check | Clifford Wolf | 2019-08-07 | 3 | -9/+17 |
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| * | | | Be less aggressive with running design->check() | Clifford Wolf | 2019-08-06 | 3 | -9/+17 |
* | | | | Tweak default gate costs, cleanup "stat -tech cmos" | Clifford Wolf | 2019-08-07 | 1 | -4/+4 |
* | | | | Redesign of cell cost API | Clifford Wolf | 2019-08-07 | 1 | -71/+77 |
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* | | | Add support for writing gzip-compressed files | David Shah | 2019-08-06 | 1 | -7/+60 |
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* | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 7 | -9/+46 |
* | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-01 | 1 | -0/+4 |
* | | Fix case when file does not exist | Miodrag Milanovic | 2019-07-29 | 1 | -19/+21 |
* | | Merge pull request #1226 from YosysHQ/dave/gzip | David Shah | 2019-07-27 | 2 | -9/+52 |
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| * | | Fix frontend auto-detection for gzipped input | David Shah | 2019-07-26 | 1 | -9/+12 |
| * | | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 1 | -0/+40 |
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* | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 |
* | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 2 | -2/+19 |
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* | Revert "Add log_checkpoint function and use it in opt_muxtree" | Eddie Hung | 2019-07-15 | 2 | -8/+0 |
* | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ... | Clifford Wolf | 2019-07-15 | 1 | -6/+13 |
* | Add log_checkpoint function and use it in opt_muxtree | Clifford Wolf | 2019-07-15 | 2 | -0/+8 |
* | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -1/+1 |
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| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -1/+1 |
* | | Clarify script -scriptwire doc | Eddie Hung | 2019-07-08 | 1 | -0/+4 |
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* | Use Pass::call_on_module() as per @cliffordwolf comments | Eddie Hung | 2019-07-02 | 1 | -1/+1 |
* | script -select -> script -scriptwire | Eddie Hung | 2019-07-02 | 1 | -5/+5 |
* | Support ability for "script -select" to take commands from wires | Eddie Hung | 2019-06-28 | 1 | -8/+39 |
* | Merge pull request #1098 from YosysHQ/xaig | Eddie Hung | 2019-06-28 | 1 | -0/+12 |
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| * | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 |
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 1 | -0/+1 |
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| * \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-20 | 2 | -1/+32 |
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| * | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 2 | -2/+11 |
| * | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -0/+6 |
| * | | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 1 | -157/+0 |
| * | | | More slimming | Eddie Hung | 2019-06-13 | 1 | -35/+35 |
| * | | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 1 | -0/+157 |
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 9 | -21/+187 |
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| * | | | | Remove kernel/cost.cc since master has refactored it | Eddie Hung | 2019-04-22 | 1 | -75/+0 |