Merge remote-tracking branch 'origin/master' into eddie/cleanup

5 files changed, 96 insertions, 80 deletions

diff --git a/kernel/cost.h b/kernel/cost.h
index e8e077ff5..10fa50fb3 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -24,86 +24,92 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false);
-
-inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters = dict<RTLIL::IdString, RTLIL::Const>(),
-		RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false)
+struct CellCosts
 {
-	static dict<RTLIL::IdString, int> gate_cost = {
-		{ "$_BUF_",    1 },
-		{ "$_NOT_",    2 },
-		{ "$_AND_",    4 },
-		{ "$_NAND_",   4 },
-		{ "$_OR_",     4 },
-		{ "$_NOR_",    4 },
-		{ "$_ANDNOT_", 4 },
-		{ "$_ORNOT_",  4 },
-		{ "$_XOR_",    8 },
-		{ "$_XNOR_",   8 },
-		{ "$_AOI3_",   6 },
-		{ "$_OAI3_",   6 },
-		{ "$_AOI4_",   8 },
-		{ "$_OAI4_",   8 },
-		{ "$_MUX_",    4 },
-		{ "$_NMUX_",   4 }
-	};
-
-	// match costs in "stat -tech cmos"
-	static dict<RTLIL::IdString, int> cmos_gate_cost = {
-		{ "$_BUF_",     1 },
-		{ "$_NOT_",     2 },
-		{ "$_AND_",     6 },
-		{ "$_NAND_",    4 },
-		{ "$_OR_",      6 },
-		{ "$_NOR_",     4 },
-		{ "$_ANDNOT_",  6 },
-		{ "$_ORNOT_",   6 },
-		{ "$_XOR_",    12 },
-		{ "$_XNOR_",   12 },
-		{ "$_AOI3_",    6 },
-		{ "$_OAI3_",    6 },
-		{ "$_AOI4_",    8 },
-		{ "$_OAI4_",    8 },
-		{ "$_MUX_",    12 },
-		{ "$_NMUX_",   10 }
-	};
-
-	if (cmos_cost && cmos_gate_cost.count(type))
-		return cmos_gate_cost.at(type);
-
-	if (gate_cost.count(type))
-		return gate_cost.at(type);
-
-	if (parameters.empty() && design && design->module(type))
+	static const dict<RTLIL::IdString, int>& default_gate_cost() {
+		static const dict<RTLIL::IdString, int> db = {
+			{ "$_BUF_",    1 },
+			{ "$_NOT_",    2 },
+			{ "$_AND_",    4 },
+			{ "$_NAND_",   4 },
+			{ "$_OR_",     4 },
+			{ "$_NOR_",    4 },
+			{ "$_ANDNOT_", 4 },
+			{ "$_ORNOT_",  4 },
+			{ "$_XOR_",    5 },
+			{ "$_XNOR_",   5 },
+			{ "$_AOI3_",   6 },
+			{ "$_OAI3_",   6 },
+			{ "$_AOI4_",   7 },
+			{ "$_OAI4_",   7 },
+			{ "$_MUX_",    4 },
+			{ "$_NMUX_",   4 }
+		};
+		return db;
+	}
+
+	static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
+		static const dict<RTLIL::IdString, int> db = {
+			{ "$_BUF_",     1 },
+			{ "$_NOT_",     2 },
+			{ "$_AND_",     6 },
+			{ "$_NAND_",    4 },
+			{ "$_OR_",      6 },
+			{ "$_NOR_",     4 },
+			{ "$_ANDNOT_",  6 },
+			{ "$_ORNOT_",   6 },
+			{ "$_XOR_",    12 },
+			{ "$_XNOR_",   12 },
+			{ "$_AOI3_",    6 },
+			{ "$_OAI3_",    6 },
+			{ "$_AOI4_",    8 },
+			{ "$_OAI4_",    8 },
+			{ "$_MUX_",    12 },
+			{ "$_NMUX_",   10 }
+		};
+		return db;
+	}
+
+	dict<RTLIL::IdString, int> mod_cost_cache;
+	const dict<RTLIL::IdString, int> *gate_cost = nullptr;
+	Design *design = nullptr;
+
+	int get(RTLIL::IdString type) const
 	{
-		RTLIL::Module *mod = design->module(type);
+		if (gate_cost && gate_cost->count(type))
+			return gate_cost->at(type);
 
-		if (mod->attributes.count("\\cost"))
-			return mod->attributes.at("\\cost").as_int();
+		log_warning("Can't determine cost of %s cell.\n", log_id(type));
+		return 1;
+	}
 
-		dict<RTLIL::IdString, int> local_mod_cost_cache;
-		if (mod_cost_cache == nullptr)
-			mod_cost_cache = &local_mod_cost_cache;
+	int get(RTLIL::Cell *cell)
+	{
+		if (gate_cost && gate_cost->count(cell->type))
+			return gate_cost->at(cell->type);
 
-		if (mod_cost_cache->count(mod->name))
-			return mod_cost_cache->at(mod->name);
+		if (design && design->module(cell->type) && cell->parameters.empty())
+		{
+			RTLIL::Module *mod = design->module(cell->type);
 
-		int module_cost = 1;
-		for (auto c : mod->cells())
-			module_cost += get_cell_cost(c, mod_cost_cache);
+			if (mod->attributes.count("\\cost"))
+				return mod->attributes.at("\\cost").as_int();
 
-		(*mod_cost_cache)[mod->name] = module_cost;
-		return module_cost;
-	}
+			if (mod_cost_cache.count(mod->name))
+				return mod_cost_cache.at(mod->name);
 
-	log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
-	return 1;
-}
+			int module_cost = 1;
+			for (auto c : mod->cells())
+				module_cost += get(c);
 
-inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache, bool cmos_cost)
-{
-	return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost);
-}
+			mod_cost_cache[mod->name] = module_cost;
+			return module_cost;
+		}
+
+		log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
+		return 1;
+	}
+};
 
 YOSYS_NAMESPACE_END
 
diff --git a/kernel/driver.cc b/kernel/driver.cc
index f273057dd..70a97c4b9 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -522,6 +522,12 @@ int main(int argc, char **argv)
 	if (!backend_command.empty())
 		run_backend(output_filename, backend_command);
 
+	yosys_design->check();
+	for (auto it : saved_designs)
+		it.second->check();
+	for (auto it : pushed_designs)
+		it->check();
+
 	if (!depsfile.empty())
 	{
 		FILE *f = fopen(depsfile.c_str(), "wt");
diff --git a/kernel/register.cc b/kernel/register.cc
index 4f60338e9..e4237cac4 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -295,8 +295,6 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
 	pass_register[args[0]]->post_execute(state);
 	while (design->selection_stack.size() > orig_sel_stack_pos)
 		design->selection_stack.pop_back();
-
-	design->check();
 }
 
 void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
@@ -378,8 +376,10 @@ void ScriptPass::run(std::string command, std::string info)
 			log("        %s\n", command.c_str());
 		else
 			log("        %s    %s\n", command.c_str(), info.c_str());
-	} else
+	} else {
 		Pass::call(active_design, command);
+		active_design->check();
+	}
 }
 
 void ScriptPass::run_script(RTLIL::Design *design, std::string run_from, std::string run_to)
@@ -573,8 +573,6 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string
 			args.push_back(filename);
 		frontend_register[args[0]]->execute(args, design);
 	}
-
-	design->check();
 }
 
 Backend::Backend(std::string name, std::string short_help) :
@@ -698,8 +696,6 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
 
 	while (design->selection_stack.size() > orig_sel_stack_pos)
 		design->selection_stack.pop_back();
-
-	design->check();
 }
 
 static struct CellHelpMessages {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 275b0b269..99c683974 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -792,6 +792,7 @@ public:
 	RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
 	RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
 	RTLIL::SigSpec extract(int offset, int length = 1) const;
+	RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
 
 	void append(const RTLIL::SigSpec &signal);
 	void append_bit(const RTLIL::SigBit &bit);
@@ -838,6 +839,7 @@ public:
 
 	operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
 	operator std::vector<RTLIL::SigBit>() const { return bits(); }
+	RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
 
 	unsigned int hash() const { if (!hash_) updhash(); return hash_; };
 
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 191b6d5c7..a4cc53f1a 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -964,14 +964,18 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 					command += next_line;
 				}
 				handle_label(command, from_to_active, run_from, run_to);
-				if (from_to_active)
+				if (from_to_active) {
 					Pass::call(design, command);
+					design->check();
+				}
 			}
 
 			if (!command.empty()) {
 				handle_label(command, from_to_active, run_from, run_to);
-				if (from_to_active)
+				if (from_to_active) {
 					Pass::call(design, command);
+					design->check();
+				}
 			}
 		}
 		catch (...) {
@@ -1000,6 +1004,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 		Pass::call(design, vector<string>({command, filename}));
 	else
 		Frontend::frontend_call(design, NULL, filename, command);
+	design->check();
 }
 
 void run_frontend(std::string filename, std::string command, RTLIL::Design *design)
@@ -1183,6 +1188,7 @@ void shell(RTLIL::Design *design)
 				design->selection_stack.pop_back();
 			log_reset_stack();
 		}
+		design->check();
 	}
 	if (command == NULL)
 		printf("exit\n");