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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:25:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:25:11 -0700 |
| commit | 84f52aee0d01378796792c9a2f068a22d955f586 (patch) | |
| tree | 2b5e6584458501d9b03d9e98c4929a1437b365d0 /kernel | |
| parent | 0b56be8c5634f8b953cd3d087b4b6e2a11a2c173 (diff) | |
| download | yosys-84f52aee0d01378796792c9a2f068a22d955f586.tar.gz yosys-84f52aee0d01378796792c9a2f068a22d955f586.tar.bz2 yosys-84f52aee0d01378796792c9a2f068a22d955f586.zip | |
Add SigSpec::extract_end() convenience function
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 633cb51d6..c07d39c65 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -788,6 +788,7 @@ public: RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; + RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); |