Merge pull request #1098 from YosysHQ/xaig

"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)

1 files changed, 12 insertions, 0 deletions

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8509670ff..f4fcf5dcf 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -276,6 +276,18 @@ namespace RTLIL
 				return std::string(c_str() + pos, len);
 		}
 
+		bool begins_with(const char* prefix) const {
+			size_t len = strlen(prefix);
+			if (size() < len) return false;
+			return substr(0, len) == prefix;
+		}
+
+		bool ends_with(const char* suffix) const {
+			size_t len = strlen(suffix);
+			if (size() < len) return false;
+			return substr(size()-len) == suffix;
+		}
+
 		size_t size() const {
 			return str().size();
 		}