| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Add support for writing gzip-compressed files | David Shah | 2019-08-06 | 1 | -7/+60 | |
| |/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 7 | -9/+46 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-01 | 1 | -0/+4 | |
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| * | | Fix case when file does not exist | Miodrag Milanovic | 2019-07-29 | 1 | -19/+21 | |
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| * | | Merge pull request #1226 from YosysHQ/dave/gzip | David Shah | 2019-07-27 | 2 | -9/+52 | |
| |\ \ | | | | | | | Add support for gzip'd input files | |||||
| | * | | Fix frontend auto-detection for gzipped input | David Shah | 2019-07-26 | 1 | -9/+12 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 1 | -0/+40 | |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 | |
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| * | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 2 | -2/+19 | |
| |/ | | | | this makes it possible to use std algorithms on them | |||||
| * | Revert "Add log_checkpoint function and use it in opt_muxtree" | Eddie Hung | 2019-07-15 | 2 | -8/+0 | |
| | | | | | This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574. | |||||
| * | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ↵ | Clifford Wolf | 2019-07-15 | 1 | -6/+13 | |
| | | | | | | | fixes #1178 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add log_checkpoint function and use it in opt_muxtree | Clifford Wolf | 2019-07-15 | 2 | -0/+8 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -1/+1 | |
| |\ | | | | | Allow attributes on individual switch cases in RTLIL | |||||
| | * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. | |||||
| * | | Clarify script -scriptwire doc | Eddie Hung | 2019-07-08 | 1 | -0/+4 | |
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| * | Use Pass::call_on_module() as per @cliffordwolf comments | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
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| * | script -select -> script -scriptwire | Eddie Hung | 2019-07-02 | 1 | -5/+5 | |
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| * | Support ability for "script -select" to take commands from wires | Eddie Hung | 2019-06-28 | 1 | -8/+39 | |
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| * | Merge pull request #1098 from YosysHQ/xaig | Eddie Hung | 2019-06-28 | 1 | -0/+12 | |
| |\ | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) | |||||
| | * | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 | |
| | | | | | | | | | invalidate | |||||
| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 1 | -0/+1 | |
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| | * \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-20 | 2 | -1/+32 | |
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| | * | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 2 | -2/+11 | |
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| | * | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -0/+6 | |
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| | * | | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 1 | -157/+0 | |
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| | * | | | More slimming | Eddie Hung | 2019-06-13 | 1 | -35/+35 | |
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| | * | | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 1 | -0/+157 | |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 9 | -21/+187 | |
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| | * | | | | Remove kernel/cost.cc since master has refactored it | Eddie Hung | 2019-04-22 | 1 | -75/+0 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 9 | -5/+289 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 2 | -3/+6 | |
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| | * | | | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| | * | | | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 2 | -3/+7 | |
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| | * \ \ \ \ \ \ | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 7 | -27/+151 | |
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| | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 1 | -2/+16 | |
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| | * | | | | | | | | | Add IdString::ends_with() | Eddie Hung | 2019-02-26 | 1 | -0/+6 | |
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| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 1 | -0/+3 | |
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| | * | | | | | | | | | | Refactor kernel/cost.h definition into cost.cc | Eddie Hung | 2019-02-08 | 2 | -49/+77 | |
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| * | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-27 | 1 | -0/+1 | |
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| | * | | | | | | | | | | Add a few more filename rewrites | Ben Widawsky | 2019-06-20 | 1 | -0/+1 | |
| | | |_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| * | | | | | | | | | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into ↵ | Clifford Wolf | 2019-06-20 | 1 | -5/+4 | |
| |\ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | clifford/ext1046 | |||||
| | * | | | | | | | | | Move netlist helper module to passes/opt for the time being | Bogdan Vukobratovic | 2019-06-14 | 1 | -317/+0 | |
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| | * | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-14 | 3 | -1/+14 | |
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| | * | | | | | | | | | Prepare for situation when port of the signal cannot be found | Bogdan Vukobratovic | 2019-06-14 | 1 | -1/+7 | |
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| | * | | | | | | | | | Implement disconnection of constant register bits | Bogdan Vukobratovic | 2019-06-13 | 1 | -32/+85 | |
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| | * | | | | | | | | | Pass SigBit by value to Netlist algorithms | Bogdan Vukobratovic | 2019-06-13 | 1 | -65/+84 | |
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| | * | | | | | | | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoring | Bogdan Vukobratovic | 2019-06-12 | 3 | -206/+243 | |
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| | * | | | | | | | | | Generate satgen instance instead of calling sat pass | Bogdan Vukobratovic | 2019-06-11 | 1 | -1/+44 | |
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| | * | | | | | | | | | Refactor driver map generation | Bogdan Vukobratovic | 2019-06-10 | 1 | -0/+158 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implement iterators over the driver map that enumerate signals and cells within the cones of the signal | |||||
| * | | | | | | | | | | Merge pull request #1100 from bwidawsk/home | Clifford Wolf | 2019-06-19 | 1 | -0/+4 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Support ~ in filename parsing | |||||
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