aboutsummaryrefslogtreecommitdiffstats
path: root/kernel
Commit message (Expand)AuthorAgeFilesLines
* New mxe hacks needed to support 2ca237eMiodrag Milanovic2019-08-011-0/+4
* Fix case when file does not existMiodrag Milanovic2019-07-291-19/+21
* Merge pull request #1226 from YosysHQ/dave/gzipDavid Shah2019-07-272-9/+52
|\
| * Fix frontend auto-detection for gzipped inputDavid Shah2019-07-261-9/+12
| * Add support for reading gzip'd input filesDavid Shah2019-07-261-0/+40
* | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
* | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-242-2/+19
|/
* Revert "Add log_checkpoint function and use it in opt_muxtree"Eddie Hung2019-07-152-8/+0
* Redesign log_id_cache so that it doesn't keep IdString instances referenced, ...Clifford Wolf2019-07-151-6/+13
* Add log_checkpoint function and use it in opt_muxtreeClifford Wolf2019-07-152-0/+8
* Merge pull request #1162 from whitequark/rtlil-case-attrsClifford Wolf2019-07-091-1/+1
|\
| * Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-1/+1
* | Clarify script -scriptwire docEddie Hung2019-07-081-0/+4
|/
* Use Pass::call_on_module() as per @cliffordwolf commentsEddie Hung2019-07-021-1/+1
* script -select -> script -scriptwireEddie Hung2019-07-021-5/+5
* Support ability for "script -select" to take commands from wiresEddie Hung2019-06-281-8/+39
* Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-281-0/+12
|\
| * Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-272-11/+2
| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-0/+1
| |\
| * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-202-1/+32
| |\ \
| * | | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-172-2/+11
| * | | Further cleanup based on @daveshah1Eddie Hung2019-06-141-0/+6
| * | | Move ConstEvalAig to aigerparse.ccEddie Hung2019-06-131-157/+0
| * | | More slimmingEddie Hung2019-06-131-35/+35
| * | | Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-0/+157
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-129-21/+187
| |\ \ \
| * | | | Remove kernel/cost.cc since master has refactored itEddie Hung2019-04-221-75/+0
| * | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-229-5/+289
| |\ \ \ \
| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-3/+6
| |\ \ \ \ \
| * | | | | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
| * | | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaigEddie Hung2019-04-182-3/+7
| |\ \ \ \ \ \
| * \ \ \ \ \ \ Merge branch 'master' into xaigEddie Hung2019-04-087-27/+151
| |\ \ \ \ \ \ \
| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-261-2/+16
| |\ \ \ \ \ \ \ \
| * | | | | | | | | Add IdString::ends_with()Eddie Hung2019-02-261-0/+6
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-211-0/+3
| |\ \ \ \ \ \ \ \ \
| * | | | | | | | | | Refactor kernel/cost.h definition into cost.ccEddie Hung2019-02-082-49/+77
* | | | | | | | | | | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-271-0/+1
|\ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|/ | |/| | | | | | | | |
| * | | | | | | | | | Add a few more filename rewritesBen Widawsky2019-06-201-0/+1
| | |_|_|_|_|_|_|_|/ | |/| | | | | | | |
* | | | | | | | | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext...Clifford Wolf2019-06-201-5/+4
|\ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / |/| | | | | | | | |
| * | | | | | | | | Move netlist helper module to passes/opt for the time beingBogdan Vukobratovic2019-06-141-317/+0
| * | | | | | | | | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-143-1/+14
| |\ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|/ | | |/| | | | | | |
| * | | | | | | | | Prepare for situation when port of the signal cannot be foundBogdan Vukobratovic2019-06-141-1/+7
| * | | | | | | | | Implement disconnection of constant register bitsBogdan Vukobratovic2019-06-131-32/+85
| * | | | | | | | | Pass SigBit by value to Netlist algorithmsBogdan Vukobratovic2019-06-131-65/+84
| * | | | | | | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoringBogdan Vukobratovic2019-06-123-206/+243
| * | | | | | | | | Generate satgen instance instead of calling sat passBogdan Vukobratovic2019-06-111-1/+44
| * | | | | | | | | Refactor driver map generationBogdan Vukobratovic2019-06-101-0/+158
* | | | | | | | | | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-191-0/+4
|\ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
| | |/ / / / / / / / | |/| | | | | | | |
* / | | | | | | | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
|/ / / / / / / / /
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-22 04:29:47 +0000