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| * Removed semicolon from macroMiodrag Milanovic2021-11-051-1/+1
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| * dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-272-7/+202
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| * verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-253-0/+7
| | | | | | | | | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
| * Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-3/+3
| | | | | | | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
| * Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
| | | | | | | | Also fixes some completely broken code in extract_reduce.
| * Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-1/+1
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| * FfData: some refactoring.Marcelina Kościelnicka2021-10-074-453/+604
| | | | | | | | | | | | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
| * Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+41
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| * kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-024-152/+275
| | | | | | | | | | | | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
| * Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-024-0/+130
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| * simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-021-3/+6
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| * Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
| | | | | | | | Fixes #2967.
| * Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-134-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-5/+5
| | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary.
| * Add v2 memory cells.Marcelina Kościelnicka2021-08-114-137/+312
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| * kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-112-21/+333
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| * Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-093-2/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
| * memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-284-6/+52
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| * kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-132-0/+79
| | | | | | | | | | | | | | While this helper is already useful to squash sequential initializations into one in cxxrtl, its main purpose is to squash overlapping masked memory initializations (when they land) and avoid having to deal with them in cxxrtl runtime.
| * kernel/mem: Use delayed removal for inits as well.Marcelina Kościelnicka2021-07-122-4/+20
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| * kernel/mem: Add documentation for more helper functions.Marcelina Kościelnicka2021-07-121-0/+34
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| * kernel/mem: Commit new values of attributes in emit.Marcelina Kościelnicka2021-07-121-0/+4
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| * kernel/mem: Make the Mem helpers inherit from AttrObject.Marcelina Kościelnicka2021-07-121-8/+4
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| * rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-123-3/+48
| | | | | | | | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
| * Fix WASI build after commit 1d88bea1.whitequark2021-06-191-1/+1
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| * pyosys: Clear SIGINT handler after Python loadsgatecat2021-06-161-0/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
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| * Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | | | | | | No change in behaviour, but use range-based for loops instead of iterators.
| * opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-092-0/+35
| | | | | | | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0826-27/+27
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
| * kernel/mem: Recognize some deprecated memory port configs.Marcelina Kościelnicka2021-06-011-0/+10
| | | | | | | | | | | | | | | | | | | | Transparency is meaningless for asynchronous ports, so we assume transparent == false to simplify the code in this case. Likewise, enable is meaningless, and we assume it is const-1. However, turns out that nMigen emits the former, and Verilog frontend emits the latter, so squash these issues when ingesting a $memrd cell. Fixes #2811.
| * Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-281-0/+3
| | | | | | | | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
| * kernel/mem: Add helpers for write port widening.Marcelina Kościelnicka2021-05-272-0/+57
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| * kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-262-20/+30
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| * kernel/mem: Add prepare_wr_merge helper.Marcelina Kościelnicka2021-05-262-0/+27
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| * mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-251-1/+4
| | | | | | | | | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
| * mem/extract_rdff: Add alternate transparency handling.Marcelina Kościelnicka2021-05-251-18/+80
| | | | | | | | | | | | | | | | | | | | When extracting read register from a transparent port that has an enable, reset, or initial value, the usual trick of putting a register on the address instead of data doesn't work. In this case, create soft transparency logic instead. When transparency masks land, this will also be used to handle ports that are transparent to only a subset of write ports.
| * kernel/mem: Add model support for read port init value and resets.Marcelina Kościelnicka2021-05-252-4/+73
| | | | | | | | | | | | | | Like wide port support, this is still completely unusable, and support in various passes will be gradually added later. It also has no support at all in the cell library, so attempting to create a read port with a reset or initial value will cause an assert failure for now.
| * mem/extract_rdff: Fix wire naming and wide port support.Marcelina Kościelnicka2021-05-251-6/+22
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| * kernel/mem: Add emulate_priority helper.Marcelina Kościelnicka2021-05-252-0/+44
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| * kernel/mem: Add a Mem::narrow helper to split up wide ports.Marcelina Kościelnicka2021-05-252-0/+53
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| * kernel/mem: Emit support for wide ports in packed mode.Marcelina Kościelnicka2021-05-251-30/+34
| | | | | | | | | | | | | | Since the packed cell doesn't actually support wide ports yet, we just auto-narrow them on emit. The future packed cell will add RD_WIDE_CONTINUATION and WR_WIDE_CONTINUATION parameters so the transform will be trivially reversible for proper serialization.
| * kernel/mem: Add model for wide ports.Marcelina Kościelnicka2021-05-252-6/+28
| | | | | | | | | | | | Such ports cannot actually be created or used yet, this just adds the necessary plumbing in the helper. Subsequent commits will gradually add wide port support to various yosys passes.
| * kernel/mem: Add priority_mask to model.Marcelina Kościelnicka2021-05-252-1/+47
| | | | | | | | | | | | | | | | This is going to be used to store arbitrary priority masks in the future. Right now, it is not supported by our cell library, so the priority_mask is computed from port order on helper construction, and discarded when emitted. However, this allows us to already convert helper-using passes to the new model.
| * hashlib: Add a hash for bool.Marcelina Kościelnicka2021-05-241-0/+6
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| * extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-232-2/+3
| | | | | | | | | | This is not used yet, but will be needed when read port reset/initial value support lands.
| * Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-234-2/+474
| | | | | | | | Fixes #1854.
| * kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-222-0/+13
| | | | | | | | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
| * kernel/mem: Add a check() function.Marcelina Kościelnicka2021-05-222-0/+26
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