verilog: use derived module info to elaborate cell connections

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change

3 files changed, 7 insertions, 0 deletions

diff --git a/kernel/constids.inc b/kernel/constids.inc
index 8d8e97eb7..8ccb60089 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -163,6 +163,7 @@ X(RD_TRANSPARENCY_MASK)
 X(RD_TRANSPARENT)
 X(RD_WIDE_CONTINUATION)
 X(reg)
+X(reprocess_after)
 X(S)
 X(SET)
 X(SET_POLARITY)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9fac57523..88153a380 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -941,6 +941,11 @@ void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdStrin
 	log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name));
 }
 
+bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
+{
+	return false;
+}
+
 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
 {
 	if (mayfail)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c428f3154..68481b81c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1161,6 +1161,7 @@ public:
 	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
 	virtual size_t count_id(RTLIL::IdString id);
 	virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
+	virtual bool reprocess_if_necessary(RTLIL::Design *design);
 
 	virtual void sort();
 	virtual void check();