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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-21 18:26:47 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-21 20:20:31 +0200 |
commit | 5cebf6a8efb4f1e9b836db76be0bb2a964932905 (patch) | |
tree | faac24ad43f2365ae39bf005c48e1e2e963290e2 /kernel | |
parent | 51d42cc917d66917439955616bc5a3842e5d6301 (diff) | |
download | yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.tar.gz yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.tar.bz2 yosys-5cebf6a8efb4f1e9b836db76be0bb2a964932905.zip |
Change implicit conversions from bool to Sig* to explicit.
Also fixes some completely broken code in extract_reduce.
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e072d5bd1..96982d2d9 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -756,7 +756,7 @@ struct RTLIL::SigBit SigBit(); SigBit(RTLIL::State bit); - SigBit(bool bit); + explicit SigBit(bool bit); SigBit(RTLIL::Wire *wire); SigBit(RTLIL::Wire *wire, int offset); SigBit(const RTLIL::SigChunk &chunk); @@ -838,7 +838,7 @@ public: SigSpec(const std::vector<RTLIL::SigBit> &bits); SigSpec(const pool<RTLIL::SigBit> &bits); SigSpec(const std::set<RTLIL::SigBit> &bits); - SigSpec(bool bit); + explicit SigSpec(bool bit); SigSpec(RTLIL::SigSpec &&other) { width_ = other.width_; |