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* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-032-0/+8
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* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+1
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* Added SAT undef model for $pmux and $safe_pmuxClifford Wolf2014-01-021-4/+19
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* Major rewrite of "freduce" commandClifford Wolf2014-01-021-5/+3
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* Added additional checks for A_SIGNED == B_SIGNED for cells with that constraintClifford Wolf2013-12-311-4/+11
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* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-291-11/+8
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* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-284-1/+12
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* Fixed sat handling of $eqx and $nex with unequal port widthsClifford Wolf2013-12-271-0/+2
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* Small cleanup in SatGenClifford Wolf2013-12-271-2/+0
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* Fixed sat handling of $eqx and $nex cellsClifford Wolf2013-12-271-1/+12
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-273-5/+21
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-272-0/+31
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* Added log_dump() APIClifford Wolf2013-12-201-0/+54
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* Added "sat" undef support and "sat -set-init" optionsClifford Wolf2013-12-071-13/+24
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* Fixed uninitialized const flags bugClifford Wolf2013-12-071-1/+1
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* Fixes and improvements in RTLIL::SigSpec::parseClifford Wolf2013-12-071-2/+12
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-042-4/+3
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-042-7/+39
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* Added Pass:call_newsel APIClifford Wolf2013-12-022-0/+27
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* Added "history" commandClifford Wolf2013-12-021-0/+18
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* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-291-1/+1
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* Improvements in satgen undef handlingClifford Wolf2013-11-251-73/+170
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* Improvements in satgen undef handlingClifford Wolf2013-11-251-27/+122
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* Started implementing undef handling in satgenClifford Wolf2013-11-251-25/+172
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-241-0/+1
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-242-8/+1
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-242-2/+3
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* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-231-0/+6
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* Some driver changes/fixesClifford Wolf2013-11-221-5/+5
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* Added more performance measurement infrastructureClifford Wolf2013-11-221-0/+41
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* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-221-30/+13
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* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-222-24/+119
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-1/+2
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* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-173-5/+23
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* Added information on all internal cell types to internal checkerClifford Wolf2013-11-111-0/+340
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* Call internal checker more oftenClifford Wolf2013-11-102-9/+8
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* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-092-0/+15
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* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-091-6/+5
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* More undef-propagation related fixesClifford Wolf2013-11-081-0/+5
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* Removed debug log from const_pow()Clifford Wolf2013-11-081-1/+0
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* Fixed handling of power operatorClifford Wolf2013-11-071-9/+41
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* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-071-8/+17
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* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-072-2/+2
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* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-072-0/+17
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* Improved undef handling in == and != for ConstEvalClifford Wolf2013-11-061-11/+25
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* Improved width extension with regard to undef propagationClifford Wolf2013-11-062-67/+100
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* Fixed handling of undef values in POS cells in ConstEvalClifford Wolf2013-11-061-3/+1
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* Fixed handling of undef values in MUX select input in ConstEvalClifford Wolf2013-11-061-32/+58
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* Added eval -vloghammer_report modeClifford Wolf2013-11-061-0/+3
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* Fixed sign handling in const eval of sshl and sshrClifford Wolf2013-11-051-2/+6
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