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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 20:29:07 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 20:29:07 +0100 |
| commit | 8dafecd34d772b1d9ec190b39913b236cdc8fb17 (patch) | |
| tree | 263b31c6aaa6ef8df765a2ad8c66212b414d793f /kernel | |
| parent | 4011d476469a761ed05f91d11935f8ad07f901ba (diff) | |
| download | yosys-8dafecd34d772b1d9ec190b39913b236cdc8fb17.tar.gz yosys-8dafecd34d772b1d9ec190b39913b236cdc8fb17.tar.bz2 yosys-8dafecd34d772b1d9ec190b39913b236cdc8fb17.zip | |
Added module->avail_parameters (for advanced techmap features)
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4b790cbde..5873c3694 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -257,6 +257,7 @@ struct RTLIL::Design { struct RTLIL::Module { RTLIL::IdString name; + std::set<RTLIL::IdString> avail_parameters; std::map<RTLIL::IdString, RTLIL::Wire*> wires; std::map<RTLIL::IdString, RTLIL::Memory*> memories; std::map<RTLIL::IdString, RTLIL::Cell*> cells; |