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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 18:11:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 18:11:05 +0100 |
| commit | 122b3c067b87464bd362ccce96fdeb84fa476653 (patch) | |
| tree | 24a53d48d43098b2717808f97bc38e223fba9609 /kernel | |
| parent | 1dcbba1abf28afae846bd42f49d716892ffd685c (diff) | |
| download | yosys-122b3c067b87464bd362ccce96fdeb84fa476653.tar.gz yosys-122b3c067b87464bd362ccce96fdeb84fa476653.tar.bz2 yosys-122b3c067b87464bd362ccce96fdeb84fa476653.zip | |
Fixed sat handling of $eqx and $nex with unequal port widths
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/satgen.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 67312f440..05f3310c0 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -462,6 +462,7 @@ struct SatGen if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); + extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); } @@ -486,6 +487,7 @@ struct SatGen std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == "$eqx") yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b)); |