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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-09 11:38:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-09 11:38:17 +0100 |
| commit | 18f9477e95aa57ce1659de1991117f881fa359bd (patch) | |
| tree | 6d6d205d660c0dcdf65a6fc5f1a2945f5de1dffe /kernel | |
| parent | 259cc1391e1e53455d9919af453b78198454e13a (diff) | |
| download | yosys-18f9477e95aa57ce1659de1991117f881fa359bd.tar.gz yosys-18f9477e95aa57ce1659de1991117f881fa359bd.tar.bz2 yosys-18f9477e95aa57ce1659de1991117f881fa359bd.zip | |
Added verification of SAT model to "eval -vloghammer_report" command
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/satgen.h | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 6bd633603..3c63f9168 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -53,17 +53,16 @@ struct SatGen this->prefix = prefix; } - std::vector<int> importSigSpec(RTLIL::SigSpec &sig, int timestep = -1) + std::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1) { assert(timestep < 0 || timestep > 0); - RTLIL::SigSpec s = sig; - sigmap->apply(s); - s.expand(); + sigmap->apply(sig); + sig.expand(); std::vector<int> vec; - vec.reserve(s.chunks.size()); + vec.reserve(sig.chunks.size()); - for (auto &c : s.chunks) + for (auto &c : sig.chunks) if (c.wire == NULL) { vec.push_back(c.data.as_bool() ? ez->TRUE : ez->FALSE); } else { |