| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| | |
|
| | |
|
| | |
|
| |\
| |
| | |
hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
|
| | |
| |
| |
| | |
`dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
|
| |/ |
|
| | |
|
| | |
|
| |\
| |
| | |
Split `flatten` from `techmap` and simplify it
|
| | | |
|
| |\ \
| | |
| | | |
Preserve 'signed'-ness of a verilog wire through RTLIL
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
|
| |\ \ \
| |_|/
|/| | |
Pyosys API: idict type handling
|
| | |/
| |
| |
| |
| | |
- Also, re-applied no-line-break workaround to rtlil.h to make parser
catch all methods.
|
| |\ \
| | |
| | | |
Fix modulo/remainder semantics
|
| | | | |
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
|
| |\ \ \
| |/ /
|/| | |
Restrict RTLIL::IdString to not contain whitespace or control chars
|
| | |/
| |
| |
| |
| | |
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
|
| |\ \
| | |
| | | |
Minor optimisation in Module::wire() and Module::cell()
|
| | |/
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
|
| |\ \
| | |
| | | |
Use default copy constructor for RTLIL::SigBit
|
| | |/
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).
This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
|
| |/
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.
Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.
Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
|
| |
|
|
| |
Fixes #1819, #1820.
|
| | |
|
| |
|
|
| |
And make {get,set}_src_attribute use those functions.
|
| |\
| |
| | |
kernel: include "kernel/constids.inc"
|
| | | |
|
| |/
|
|
|
|
|
|
|
| |
A few passes included the same list of FF cell types. Make it a global
const instead.
The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
|
| | |
|
| | |
|
| | |
|
| |\
| |
| | |
kernel: speedup by using more pass-by-const-ref
|
| | | |
|
| | |
| |
| |
| | |
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| |/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
