| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -0/+1 |
| * | Added some missing "const" in rtlil.h | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Added RTLIL::Module::connections() | Clifford Wolf | 2014-07-26 | 1 | -0/+1 |
| * | Added RTLIL::Module::connect(const RTLIL::SigSig&) | Clifford Wolf | 2014-07-26 | 1 | -0/+1 |
| * | Automatically pack SigSpec on copy/assign | Clifford Wolf | 2014-07-26 | 1 | -0/+3 |
| * | Added new RTLIL::Cell port access methods | Clifford Wolf | 2014-07-26 | 1 | -0/+8 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -10/+26 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -0/+1 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+19 |
| * | Added RTLIL::SigSpec is_chunk()/as_chunk() API | Clifford Wolf | 2014-07-25 | 1 | -0/+3 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -1/+3 |
| * | Small changes regarding cover() and check() in SigSpec | Clifford Wolf | 2014-07-24 | 1 | -0/+4 |
| * | Added hashing to RTLIL::SigSpec relational and equal operators | Clifford Wolf | 2014-07-23 | 1 | -2/+7 |
| * | Added RTLIL::SigSpec::repeat() | Clifford Wolf | 2014-07-23 | 1 | -0/+2 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -7/+0 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -3/+0 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -6/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+8 |
| * | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | SigSpec refactoring: Added RTLIL::SigSpecIterator | Clifford Wolf | 2014-07-22 | 1 | -6/+28 |
| * | SigSpec refactoring: added RTLIL::SigSpec::operator[] | Clifford Wolf | 2014-07-22 | 1 | -1/+4 |
| * | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 | 1 | -1/+0 |
| * | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 | 1 | -10/+32 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 | 1 | -2/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 | 1 | -3/+9 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -4/+7 |
| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -3/+0 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -5/+5 |
| * | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 | 1 | -0/+5 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 | 1 | -0/+1 |
| * | Added SIZE() macro | Clifford Wolf | 2014-07-20 | 1 | -0/+2 |
| * | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 | 1 | -0/+1 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 | 1 | -0/+55 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 | 1 | -0/+4 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 | 1 | -0/+7 |
| * | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 | 1 | -0/+6 |
| * | Added RTLIL::Module::add... helper methods | Clifford Wolf | 2014-03-10 | 1 | -0/+57 |
| * | Added generic RTLIL::SigSpec::parse_sel() with support for selection variables | Clifford Wolf | 2014-02-06 | 1 | -0/+1 |
| * | Added RTLIL::SigSpec::to_single_sigbit() | Clifford Wolf | 2014-02-02 | 1 | -0/+1 |
| * | Added select -assert-none and -assert-any | Clifford Wolf | 2014-01-17 | 1 | -0/+3 |
| * | Added RTLIL::SigSpec::optimized() API | Clifford Wolf | 2014-01-03 | 1 | -0/+1 |
| * | Added $bu0 cell (for easy correct $eq/$ne mapping) | Clifford Wolf | 2013-12-28 | 1 | -0/+1 |
| * | Added proper === and !== support in constant expressions | Clifford Wolf | 2013-12-27 | 1 | -0/+2 |
| * | Fixed uninitialized const flags bug | Clifford Wolf | 2013-12-07 | 1 | -1/+1 |
| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 | 1 | -3/+2 |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -2/+12 |
