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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:27 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:22 +0200 |
commit | cd6574ecf652901573cbc6b89e1a59dd383ec496 (patch) | |
tree | c855477b523f67df1fc1d4b9fabbfa848cbcff42 /kernel/rtlil.h | |
parent | 7ac9dc7f6eab40b3853583848933c4a8a94df9c9 (diff) | |
download | yosys-cd6574ecf652901573cbc6b89e1a59dd383ec496.tar.gz yosys-cd6574ecf652901573cbc6b89e1a59dd383ec496.tar.bz2 yosys-cd6574ecf652901573cbc6b89e1a59dd383ec496.zip |
Added some missing "const" in rtlil.h
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1775975d5..25d0a8309 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -290,7 +290,7 @@ struct RTLIL::Module void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); - const std::vector<RTLIL::SigSig> &connections(); + const std::vector<RTLIL::SigSig> &connections() const; void fixup_ports(); template<typename T> void rewrite_sigspecs(T functor); @@ -490,8 +490,8 @@ public: // access cell ports void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); - RTLIL::SigSpec get(RTLIL::IdString portname) const; - const std::map<RTLIL::IdString, RTLIL::SigSpec> &connections(); + const RTLIL::SigSpec &get(RTLIL::IdString portname) const; + const std::map<RTLIL::IdString, RTLIL::SigSpec> &connections() const; void check(); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); @@ -608,7 +608,7 @@ public: void remove(int offset, int length = 1); void remove_const(); - RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; + RTLIL::SigSpec extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; void append(const RTLIL::SigSpec &signal); |