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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
| commit | 97a59851a6c411ccb06162d4b31725bf89262378 (patch) | |
| tree | 74cba570ab858657b6fa524cdc9fa45b0493c4be /kernel/rtlil.h | |
| parent | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff) | |
| download | yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.gz yosys-97a59851a6c411ccb06162d4b31725bf89262378.tar.bz2 yosys-97a59851a6c411ccb06162d4b31725bf89262378.zip | |
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 25d0a8309..73d3727ce 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -488,6 +488,7 @@ public: RTLIL_ATTRIBUTE_MEMBERS // access cell ports + bool has(RTLIL::IdString portname); void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); const RTLIL::SigSpec &get(RTLIL::IdString portname) const; |