| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Changed NEW_WIRE API to return the wire, not the signal | Clifford Wolf | 2013-10-18 | 1 | -1/+1 |
| * | Added RTLIL NEW_WIRE macro | Clifford Wolf | 2013-10-18 | 1 | -0/+9 |
| * | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 | 1 | -0/+89 |
| * | Added "eval" pass | Clifford Wolf | 2013-06-19 | 1 | -0/+85 |
| * | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 | 1 | -2/+31 |
| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 1 | -7/+7 |
| * | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -3/+10 |
| * | Create nice errors when calling RTLIL::Module::derive() of base class | Clifford Wolf | 2013-03-26 | 1 | -3/+3 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+1081 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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