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author | Clifford Wolf <clifford@clifford.at> | 2013-06-18 17:11:13 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-06-18 17:11:13 +0200 |
commit | 6971c4db62fce93953edf5dd4fb511e9ccebdecc (patch) | |
tree | 0a8da3a733de6e290f60231f836e5eada5f40d34 /kernel/rtlil.cc | |
parent | 5cf04f33fa081ead8f0b8799eb324a3c5d4acac1 (diff) | |
download | yosys-6971c4db62fce93953edf5dd4fb511e9ccebdecc.tar.gz yosys-6971c4db62fce93953edf5dd4fb511e9ccebdecc.tar.bz2 yosys-6971c4db62fce93953edf5dd4fb511e9ccebdecc.zip |
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2c255285f..dacefa215 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -340,18 +340,47 @@ void RTLIL::Module::optimize() } } -void RTLIL::Module::add(RTLIL::Wire *wire) { +void RTLIL::Module::add(RTLIL::Wire *wire) +{ assert(!wire->name.empty()); assert(count_id(wire->name) == 0); wires[wire->name] = wire; } -void RTLIL::Module::add(RTLIL::Cell *cell) { +void RTLIL::Module::add(RTLIL::Cell *cell) +{ assert(!cell->name.empty()); assert(count_id(cell->name) == 0); cells[cell->name] = cell; } +static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) +{ + if (a->port_id && !b->port_id) + return true; + if (!a->port_id && b->port_id) + return false; + + if (a->port_id == b->port_id) + return a->name < b->name; + return a->port_id < b->port_id; +} + +void RTLIL::Module::fixup_ports() +{ + std::vector<RTLIL::Wire*> all_ports; + + for (auto &w : wires) + if (w.second->port_input || w.second->port_output) + all_ports.push_back(w.second); + else + w.second->port_id = 0; + + std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare); + for (size_t i = 0; i < all_ports.size(); i++) + all_ports[i]->port_id = i+1; +} + RTLIL::Wire::Wire() { width = 1; |