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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 14:19:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 14:19:45 +0200 |
| commit | 8e8f1994b837e19dfa9362110dee34f1099d2c4d (patch) | |
| tree | bdb024d5b929db84d8534492f84450cef8cabc55 /kernel/rtlil.cc | |
| parent | bfa1a65fa9de21f96419bb7d947a57d5e2d7f9e6 (diff) | |
| download | yosys-8e8f1994b837e19dfa9362110dee34f1099d2c4d.tar.gz yosys-8e8f1994b837e19dfa9362110dee34f1099d2c4d.tar.bz2 yosys-8e8f1994b837e19dfa9362110dee34f1099d2c4d.zip | |
Changed NEW_WIRE API to return the wire, not the signal
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5075215cd..7bd67e08f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -382,7 +382,7 @@ RTLIL::Module *RTLIL::Module::clone() const return new_mod; } -RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name) +RTLIL::Wire *RTLIL::Module::new_wire(int width, RTLIL::IdString name) { RTLIL::Wire *wire = new RTLIL::Wire; wire->width = width; |