iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-1/+16
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-5/+2
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-8/+8
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-4/+4
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-4/+4
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-9/+9
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-9/+9
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-3/+3
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-5/+2
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03	1	-4/+6
*	Fixed handling of undef values in MUX select input in ConstEval	Clifford Wolf	2013-11-06	1	-32/+58
*	initial import	Clifford Wolf	2013-01-05	1	-0/+198