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authorClifford Wolf <clifford@clifford.at>2014-08-16 18:18:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 18:29:39 +0200
commit47c2637a961839f1eb1a0386f7e54d94be50bc10 (patch)
tree2db3bfbabf1ad7ca21176c2639b565720655fb8b /kernel/consteval.h
parent56a30cf42c6a40f265a67df6e2c5fa74657fbf5b (diff)
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
Diffstat (limited to 'kernel/consteval.h')
-rw-r--r--kernel/consteval.h17
1 files changed, 16 insertions, 1 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h
index dbe13ea7e..d42c2b0f1 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -156,11 +156,26 @@ struct ConstEval
}
else
{
+ RTLIL::SigSpec sig_c, sig_d;
+
+ if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) {
+ if (cell->hasPort("\\C"))
+ sig_c = cell->getPort("\\C");
+ if (cell->hasPort("\\D"))
+ sig_d = cell->getPort("\\D");
+ }
+
if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
return false;
if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
return false;
- set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const()));
+ if (sig_c.size() > 0 && !eval(sig_c, undef, cell))
+ return false;
+ if (sig_d.size() > 0 && !eval(sig_d, undef, cell))
+ return false;
+
+ set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(),
+ sig_c.as_const(), sig_d.as_const()));
}
return true;