| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Use more ID::{A,B,Y,blackbox,whitebox} | Eddie Hung | 2019-08-15 | 1 | -8/+8 |
| * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) | Clifford Wolf | 2019-08-11 | 1 | -33/+33 |
| * | RTLIL::S{0,1} -> State::S{0,1} for headers | Eddie Hung | 2019-08-07 | 1 | -11/+11 |
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -2/+5 |
| * | Improve ConstEval error handling for non-eval cell types | Clifford Wolf | 2018-11-29 | 1 | -2/+7 |
| * | Add ConstEval defaultval feature | Clifford Wolf | 2017-04-05 | 1 | -1/+8 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -10/+10 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Simplified $fa undef model | Clifford Wolf | 2014-09-08 | 1 | -0/+4 |
| * | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+37 |
| * | Added "$fa" cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+25 |
| * | Added $macc eval model | Clifford Wolf | 2014-09-06 | 1 | -0/+22 |
| * | Fixes in $alu SAT- and eval-models | Clifford Wolf | 2014-09-03 | 1 | -2/+2 |
| * | Added ConstEval model for $alu cells | Clifford Wolf | 2014-09-01 | 1 | -0/+56 |
| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 1 | -1/+16 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -5/+2 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -8/+8 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -4/+4 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -9/+9 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -9/+9 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -3/+3 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -5/+2 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux | Clifford Wolf | 2014-01-03 | 1 | -4/+6 |
| * | Fixed handling of undef values in MUX select input in ConstEval | Clifford Wolf | 2013-11-06 | 1 | -32/+58 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+198 |
