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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
| commit | 52355f5185fe42e28775e897f458b38a439c0ec5 (patch) | |
| tree | 83d8984e70806c9bcc8cd6d72ea81456ca76aba6 /kernel/consteval.h | |
| parent | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (diff) | |
| download | yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.gz yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.bz2 yosys-52355f5185fe42e28775e897f458b38a439c0ec5.zip | |
Use more ID::{A,B,Y,blackbox,whitebox}
Diffstat (limited to 'kernel/consteval.h')
| -rw-r--r-- | kernel/consteval.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index 09b4c434b..7a83d28e7 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -128,8 +128,8 @@ struct ConstEval RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - log_assert(cell->hasPort(ID(Y))); - sig_y = values_map(assign_map(cell->getPort(ID(Y)))); + log_assert(cell->hasPort(ID::Y)); + sig_y = values_map(assign_map(cell->getPort(ID::Y))); if (sig_y.is_fully_const()) return true; @@ -139,11 +139,11 @@ struct ConstEval return false; } - if (cell->hasPort(ID(A))) - sig_a = cell->getPort(ID(A)); + if (cell->hasPort(ID::A)) + sig_a = cell->getPort(ID::A); - if (cell->hasPort(ID(B))) - sig_b = cell->getPort(ID(B)); + if (cell->hasPort(ID::B)) + sig_b = cell->getPort(ID::B); if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { @@ -298,11 +298,11 @@ struct ConstEval return false; } - RTLIL::Const result(0, GetSize(cell->getPort(ID(Y)))); + RTLIL::Const result(0, GetSize(cell->getPort(ID::Y))); if (!macc.eval(result)) log_abort(); - set(cell->getPort(ID(Y)), result); + set(cell->getPort(ID::Y), result); } else { |