aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/celltypes.h
Commit message (Expand)AuthorAgeFilesLines
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-051-2/+10
* Added $assume cell typeClifford Wolf2015-02-261-0/+1
* Added $meminit cell typeClifford Wolf2015-02-141-0/+1
* Added $equiv cell typeClifford Wolf2015-01-191-0/+1
* Added global yosys_celltypesClifford Wolf2014-12-291-40/+57
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-281-6/+6
* Added functionality to dff2dffe passClifford Wolf2014-12-081-0/+1
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-081-0/+4
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-6/+6
* Added $_BUF_ cell typeClifford Wolf2014-10-031-0/+3
* Added $lcu cell typeClifford Wolf2014-09-081-0/+1
* Added "$fa" cell typeClifford Wolf2014-09-081-0/+1
* Added $macc cell typeClifford Wolf2014-09-061-6/+5
* Removed $bu0 cell typeClifford Wolf2014-09-041-3/+2
* Added eval model for $lut cellsClifford Wolf2014-08-311-0/+26
* Added $alu cell typeClifford Wolf2014-08-301-0/+2
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-221-2/+2
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-6/+43
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+1
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Added module->portsClifford Wolf2014-08-141-1/+2
* Refactoring of CellType classClifford Wolf2014-08-141-135/+105
* RIP $safe_pmuxClifford Wolf2014-08-141-2/+1
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-021-5/+5
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-1/+5
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-7/+7
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-4/+4
* Added support for dlatchsr cellsClifford Wolf2014-03-311-0/+9
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-271-1/+1
* Added $slice and $concat to CellTypes listClifford Wolf2014-02-071-0/+2
* Added $slice and $concat cell typesClifford Wolf2014-02-071-4/+15
* Added $assert cellClifford Wolf2014-01-191-0/+1
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-281-0/+2
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-0/+4
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+14
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-1/+3
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-231-0/+3
* Fixed even more ConstEval bugs found using xsthammerClifford Wolf2013-06-141-2/+5
* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-131-0/+8
* Added log_assert() apiClifford Wolf2013-05-241-2/+4
* Added additional functionality and cleanups in sigtools.h and celltypes.hClifford Wolf2013-03-151-0/+9
* Added #ci and #co selection operatorsClifford Wolf2013-03-141-5/+15
* Added $sr cell type to celltypes.hClifford Wolf2013-03-141-0/+1
* Added library support to celltypes class and show passClifford Wolf2013-03-031-4/+35
* initial importClifford Wolf2013-01-051-0/+210