diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:13:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:22:52 +0200 |
| commit | 1bf7a18fec76cf46a5b8710a75371e23b68d147d (patch) | |
| tree | ea445edda6c4bc0fa670effce4ef1b0eaf906258 /kernel/celltypes.h | |
| parent | 746aac540b815099c6a63077010555369d7fdd5a (diff) | |
| download | yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.gz yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.bz2 yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.zip | |
Added module->ports
Diffstat (limited to 'kernel/celltypes.h')
| -rw-r--r-- | kernel/celltypes.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6beaa3fed..5486f6acb 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -67,7 +67,8 @@ struct CellTypes void setup_module(RTLIL::Module *module) { std::set<RTLIL::IdString> inputs, outputs; - for (auto wire : module->wires()) { + for (RTLIL::IdString wire_name : module->ports) { + RTLIL::Wire *wire = module->wire(wire_name); if (wire->port_input) inputs.insert(wire->name); if (wire->port_output) |