index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
Fixed cstr_buf for std::string with small string optimization
Clifford Wolf
2015-06-11
6
-5
/
+16
*
Improvements in cellaigs.cc and "json -aig"
Clifford Wolf
2015-06-11
2
-10
/
+215
*
AigMaker refactoring
Clifford Wolf
2015-06-10
4
-78
/
+153
*
Added "json -aig"
Clifford Wolf
2015-06-10
3
-9
/
+76
*
Renamed "aig" to "aigmap"
Clifford Wolf
2015-06-10
3
-10
/
+10
*
Fixed cellaigs port extending
Clifford Wolf
2015-06-10
3
-3
/
+11
*
Added "aig" pass
Clifford Wolf
2015-06-09
3
-16
/
+291
*
synth_ice40 now flattens by default
Clifford Wolf
2015-06-09
1
-4
/
+8
*
Added cellaigs API
Clifford Wolf
2015-06-09
4
-2
/
+173
*
Merge clock inverters in memory_dff
Clifford Wolf
2015-06-09
1
-16
/
+37
*
Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys
Clifford Wolf
2015-06-09
1
-54
/
+110
|
\
|
*
$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
2
-58
/
+110
|
*
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
2
-16
/
+20
*
|
Fixed "avail_parameters" handling in module clone/copy
Clifford Wolf
2015-06-08
1
-0
/
+2
*
|
Added log_dump() support for IdStrings
Clifford Wolf
2015-06-08
2
-0
/
+5
*
|
Fixed handling of parameters with reversed range
Clifford Wolf
2015-06-08
1
-1
/
+1
|
/
*
Added opt_share -share_all
Clifford Wolf
2015-05-31
2
-16
/
+32
*
Added iCE40 PLL cells
Clifford Wolf
2015-05-31
1
-0
/
+168
*
Added liberty dont_use support to dfflibmap
Clifford Wolf
2015-05-31
1
-0
/
+4
*
Fixed signedness of genvar expressions
Clifford Wolf
2015-05-29
1
-2
/
+2
*
Added output args to synth_ice40
Clifford Wolf
2015-05-26
2
-2
/
+37
*
Improvements in BLIF front-end
Clifford Wolf
2015-05-24
2
-4
/
+51
*
improved ice40 SB_IO sim model
Clifford Wolf
2015-05-23
1
-16
/
+9
*
Improved "flatten" handlings of inout ports
Clifford Wolf
2015-05-23
1
-2
/
+26
*
Added simple $dlatch support to opt_rmdff
Clifford Wolf
2015-05-23
1
-0
/
+35
*
Added ice40 SB_IO sim model
Clifford Wolf
2015-05-23
1
-1
/
+46
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2015-05-22
1
-19
/
+23
|
\
|
*
Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
1
-19
/
+23
*
|
preserve used $-wires with init attribute in opt_clean
Clifford Wolf
2015-05-22
1
-1
/
+1
|
/
*
bugfix in blif front-end
Clifford Wolf
2015-05-18
2
-6
/
+6
*
added vloghtb test_febe.sh
Clifford Wolf
2015-05-17
2
-0
/
+49
*
Improved .latch support in BLIF front-end
Clifford Wolf
2015-05-17
1
-3
/
+30
*
Added read_blif command
Clifford Wolf
2015-05-17
2
-1
/
+33
*
Generalized blifparse API
Clifford Wolf
2015-05-17
3
-21
/
+31
*
abc/blifparse files reorganization
Clifford Wolf
2015-05-17
7
-8
/
+9
*
Verific build fixes
Clifford Wolf
2015-05-17
5
-7
/
+7
*
Added .barbuf support to abc BLIF parser
Clifford Wolf
2015-05-13
1
-0
/
+20
*
changed file() to open() in python scripts
Clifford Wolf
2015-05-11
4
-11
/
+11
*
Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
1
-1
/
+2
|
\
|
*
Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
1
-11
/
+12
*
|
Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
1
-11
/
+11
|
/
*
Merge pull request #62 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-10
1
-1
/
+164
|
\
|
*
Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
1
-22
/
+11
|
*
Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
1
-50
/
+105
|
*
Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
1
-1
/
+120
|
/
*
Fixed memory_unpack for initialized memories
Clifford Wolf
2015-04-29
1
-0
/
+17
*
Preserve important attributes in splitnets
Clifford Wolf
2015-04-29
1
-0
/
+13
*
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
4
-1
/
+38
*
ice40_opt bugfix
Clifford Wolf
2015-04-27
2
-6
/
+4
*
iCE40: SB_CARRY const fold -> unmap SB_LUT
Clifford Wolf
2015-04-27
1
-3
/
+44
[next]