| Commit message (Expand) | Author | Age | Files | Lines |
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| * | fix width detection of array querying function in case and case item expressions | Zachary Snow | 2021-12-17 | 2 | -2/+5 |
| * | preprocessor: do not destroy double slash escaped identifiers | Thomas Sailer | 2021-12-15 | 1 | -0/+10 |
| * | Add YOSYS to the implicitly defined verilog macros in verific | Claire Xenia Wolf | 2021-12-13 | 1 | -1/+2 |
| * | Merge pull request #3102 from YosysHQ/claire/enumxz | Miodrag Milanović | 2021-12-10 | 1 | -1/+1 |
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| | * | Fix verific import of enum values with x and/or z | Claire Xenia Wolf | 2021-12-10 | 1 | -1/+1 |
| * | | Update verific.cc | Claire Xen | 2021-12-10 | 1 | -4/+7 |
| * | | If direction NONE use that from first bit | Miodrag Milanovic | 2021-12-08 | 1 | -0/+7 |
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| * | Make sure cell names are unique for wide operators | Miodrag Milanovic | 2021-12-03 | 1 | -2/+2 |
| * | Support parameters using struct as a wiretype (#3050) | Kamil Rakoczy | 2021-11-16 | 1 | -7/+23 |
| * | No need to alocate more memory than used | Miodrag Milanovic | 2021-11-10 | 1 | -1/+0 |
| * | genrtlil: Fix displaying debug info in packages | Kamil Rakoczy | 2021-11-10 | 1 | -1/+2 |
| * | Add "verific -cfg" command | Claire Xenia Wolf | 2021-11-01 | 1 | -2/+75 |
| * | Fix verific gclk handling for async-load FFs | Claire Xenia Wolf | 2021-10-31 | 1 | -12/+67 |
| * | Enable async load dff emit by default in Verific | Miodrag Milanovic | 2021-10-27 | 1 | -1/+1 |
| * | Revert "Compile option for enabling async load verific support" | Miodrag Milanovic | 2021-10-27 | 1 | -4/+1 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 4 | -41/+291 |
| * | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 2 | -24/+57 |
| * | Compile option for enabling async load verific support | Miodrag Milanovic | 2021-10-25 | 1 | -1/+4 |
| * | Fix verific.cc PRIM_DLATCH handling | Claire Xenia Wolf | 2021-10-21 | 1 | -1/+7 |
| * | Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} | Claire Xenia Wolf | 2021-10-21 | 1 | -4/+55 |
| * | Option to disable verific VHDL support | Miodrag Milanovic | 2021-10-20 | 2 | -11/+45 |
| * | Support PRIM_BUFIF1 primitive | Miodrag Milanovic | 2021-10-14 | 1 | -2/+2 |
| * | Merge pull request #3039 from YosysHQ/claire/verific_aldff | Claire Xen | 2021-10-11 | 2 | -1/+91 |
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| | * | Add Verific adffe/dffsre/aldffe FIXMEs | Claire Xenia Wolf | 2021-10-11 | 1 | -0/+3 |
| | * | Fixes and add comments for open FIXME items | Claire Xenia Wolf | 2021-10-08 | 1 | -1/+34 |
| | * | Add support for $aldff flip-flops to verific importer | Claire Xenia Wolf | 2021-10-08 | 2 | -1/+55 |
| * | | Import module attributes from Verific | Miodrag Milanovic | 2021-10-10 | 1 | -0/+1 |
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| * | verific set db_infer_set_reset_registers | Miodrag Milanovic | 2021-10-04 | 1 | -0/+1 |
| * | Specify minimum bison version 3.0+ | Zachary Snow | 2021-10-01 | 2 | -0/+4 |
| * | Merge pull request #3014 from YosysHQ/claire/fix-vgtest | Claire Xen | 2021-09-24 | 1 | -0/+1 |
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| | * | Fix TOK_ID memory leak in for_initialization | Zachary Snow | 2021-09-23 | 1 | -0/+1 |
| * | | sv: support wand and wor of data types | Zachary Snow | 2021-09-21 | 1 | -9/+12 |
| * | | verilog: fix multiple AST_PREFIX scope resolution issues | Zachary Snow | 2021-09-21 | 2 | -4/+10 |
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| * | verilog: Squash flex-triggered warning. | Marcelina Kościelnicka | 2021-09-13 | 1 | -0/+2 |
| * | update required verific version | Miodrag Milanovic | 2021-09-02 | 1 | -1/+1 |
| * | sv: support declaration in generate for initialization | Zachary Snow | 2021-08-31 | 1 | -1/+95 |
| * | sv: support declaration in procedural for initialization | Zachary Snow | 2021-08-30 | 1 | -1/+48 |
| * | Make Verific extensions optional | Miodrag Milanovic | 2021-08-20 | 1 | -1/+6 |
| * | Generate an RTLIL representation of bind constructs | Rupert Swarbrick | 2021-08-13 | 6 | -2/+193 |
| * | sv: improve support for wire and var with user-defined types | Brett Witherspoon | 2021-08-12 | 1 | -11/+44 |
| * | Allow optional comma after last entry in enum | Michael Singer | 2021-08-09 | 1 | -11/+12 |
| * | verilog: Support tri/triand/trior wire types. | Marcelina Kościelnicka | 2021-08-06 | 1 | -0/+3 |
| * | Require latest verific | Miodrag Milanovic | 2021-08-02 | 1 | -1/+1 |
| * | genrtlil: add width detection for AST_PREFIX nodes | Zachary Snow | 2021-07-29 | 1 | -0/+8 |
| * | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 2 | -4/+31 |
| * | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 4 | -51/+83 |
| * | Update to latest verific | Miodrag Milanovic | 2021-07-21 | 1 | -3/+3 |
| * | Add support for parsing the SystemVerilog 'bind' construct | Rupert Swarbrick | 2021-07-16 | 5 | -4/+83 |
| * | sv: fix two struct access bugs | Zachary Snow | 2021-07-15 | 3 | -1/+10 |
| * | rtlil: Make Process handling more uniform with Cell and Wire. | Marcelina Kościelnicka | 2021-07-12 | 2 | -6/+2 |
