rtlil: Make Process handling more uniform with Cell and Wire.

- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes

2 files changed, 2 insertions, 6 deletions

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 6b119b7ff..e6f7b30c1 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -319,16 +319,14 @@ struct AST_INTERNAL::ProcessGenerator
 		LookaheadRewriter la_rewriter(always);
 
 		// generate process and simple root case
-		proc = new RTLIL::Process;
+		proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
 		set_src_attr(proc, always);
-		proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
 		for (auto &attr : always->attributes) {
 			if (attr.second->type != AST_CONSTANT)
 				log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
 						attr.first.c_str());
 			proc->attributes[attr.first] = attr.second->asAttrConst();
 		}
-		current_module->processes[proc->name] = proc;
 		current_case = &proc->root_case;
 
 		// create initial temporary signal for all output registers
diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y
index 0e6eacf88..67aeb10e0 100644
--- a/frontends/rtlil/rtlil_parser.y
+++ b/frontends/rtlil/rtlil_parser.y
@@ -283,10 +283,8 @@ proc_stmt:
 	TOK_PROCESS TOK_ID EOL {
 		if (current_module->processes.count($2) != 0)
 			rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str());
-		current_process = new RTLIL::Process;
-		current_process->name = $2;
+		current_process = current_module->addProcess($2);
 		current_process->attributes = attrbuf;
-		current_module->processes[$2] = current_process;
 		switch_stack.clear();
 		switch_stack.push_back(&current_process->root_case.switches);
 		case_stack.clear();