Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Support asymmetric memories for verific frontend | Miodrag Milanovic | 2020-06-01 | 1 | -6/+1 |
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* | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic | clairexen | 2020-05-29 | 1 | -2/+2 |
|\ | | | | | ast/simplify: don't bitblast async ROMs declared as `logic` | ||||
| * | ast/simplify: don't bitblast async ROMs declared as `logic`. | whitequark | 2020-05-05 | 1 | -2/+2 |
| | | | | | | | | Fixes #2020. | ||||
* | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erange | whitequark | 2020-05-29 | 1 | -1/+3 |
|\ \ | | | | | | | ilang_lexer: fix check for out of range literal | ||||
| * | | ilang_lexer: fix check for out of range literal. | whitequark | 2020-05-29 | 1 | -1/+3 |
| | | | | | | | | | | | | Commit ca70a104 did not use a correct check. | ||||
* | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexer | whitequark | 2020-05-29 | 1 | -6/+5 |
|\ \ \ | |/ / |/| | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. | ||||
| * | | verilog: Move lexer location variables from global namespace to ↵ | Alberto Gonzalez | 2020-05-06 | 1 | -6/+5 |
| | | | | | | | | | | | | `VERILOG_FRONTEND` namespace. | ||||
* | | | Silence spurious warning in Verilog lexer when compiling with GCC | Rupert Swarbrick | 2020-05-26 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL. | ||||
* | | | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 |
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* | | | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -2/+0 |
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* | | | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 |
| | | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay. | ||||
* | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 |
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* | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -11/+9 |
|\ \ \ | | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts) | ||||
| * | | | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 |
| | | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | ||||
| * | | | verilog: attributes before task enable (but 13 s/r conflicts) | Eddie Hung | 2020-05-14 | 1 | -10/+8 |
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* | | | | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -1/+20 |
| | | | | | | | | | | | | | | | | Fixes #2058. | ||||
* | | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff | Eddie Hung | 2020-05-18 | 2 | -4/+12 |
|\ \ \ \ | | | | | | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *) | ||||
| * | | | | aiger: -xaiger to return $_FF_ flops | Eddie Hung | 2020-05-14 | 1 | -15/+2 |
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| * | | | | aiger/xaiger: use odd for negedge clk, even for posedge | Eddie Hung | 2020-05-14 | 1 | -4/+3 |
| | | | | | | | | | | | | | | | | | | | | Since abc9 doesn't like negative mergeability values | ||||
| * | | | | aiger: -xaiger to parse initial state back into (* init *) on Q wire | Eddie Hung | 2020-05-14 | 1 | -1/+2 |
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| * | | | | aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created | Eddie Hung | 2020-05-14 | 2 | -3/+24 |
| | | | | | | | | | | | | | | | | | | | | according to mergeability class, and init state as cell attr | ||||
* | | | | | Revert "Add support for non-power-of-two mem chunks in verific importer" | Claire Wolf | 2020-05-17 | 1 | -12/+2 |
|/ / / / | | | | | | | | | | | | | This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9. | ||||
* | | | | Merge pull request #2045 from YosysHQ/eddie/fix2042 | Eddie Hung | 2020-05-14 | 1 | -1/+13 |
|\ \ \ \ | | | | | | | | | | | verilog: error if no direction given for task arguments, default to input in SV mode | ||||
| * | | | | verilog: default to input in sv mode if task/func has no dir ... | Eddie Hung | 2020-05-13 | 1 | -2/+10 |
| | | | | | | | | | | | | | | | | | | | | otherwise error | ||||
| * | | | | verilog: error out when non-ANSI task/func arguments | Eddie Hung | 2020-05-11 | 1 | -1/+5 |
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* | | | | Merge pull request #2052 from YosysHQ/claire/verific_memfix | Claire Wolf | 2020-05-14 | 1 | -2/+12 |
|\ \ \ \ | | | | | | | | | | | Add support for non-power-of-two mem chunks in verific importer | ||||
| * | | | | Add support for non-power-of-two mem chunks in verific importer | Claire Wolf | 2020-05-14 | 1 | -2/+12 |
| |/ / / | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto | Claire Wolf | 2020-05-14 | 1 | -1/+1 |
|\ \ \ \ | |/ / / |/| | | | ast: swap range regardless of range_left >= 0 | ||||
| * | | | ast: swap range regardless of range_left >= 0 | Eddie Hung | 2020-05-04 | 1 | -1/+1 |
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* | | | | Merge pull request #2022 from Xiretza/fallthroughs | whitequark | 2020-05-08 | 2 | -4/+5 |
|\ \ \ \ | | | | | | | | | | | Avoid switch fall-through warnings | ||||
| * | | | | Add YS_FALLTHROUGH macro to mark case fall-through | Xiretza | 2020-05-07 | 2 | -4/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all. | ||||
* | | | | | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 5 | -16/+82 |
|\ \ \ \ \ | |/ / / / |/| | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset | ||||
| * | | | | Fix handling of signed indices in bit slices | Claire Wolf | 2020-05-02 | 1 | -3/+8 |
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
| * | | | | Add AST_SELFSZ and improve handling of bit slices | Claire Wolf | 2020-05-02 | 5 | -7/+22 |
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
| * | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵ | Claire Wolf | 2020-05-02 | 4 | -7/+53 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | | | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 1 | -1/+6 |
|\ \ \ \ \ | |_|_|/ / |/| | | | | verilog: allow null gen-if then block | ||||
| * | | | | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 1 | -1/+6 |
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* | | | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup | Eddie Hung | 2020-05-05 | 6 | -31/+31 |
|\ \ \ \ | | | | | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | ||||
| * | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 6 | -31/+31 |
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* | | | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 2 | -2/+6 |
|\ \ \ \ | | | | | | | | | | | verilog: set src attribute for primitives | ||||
| * | | | | verilog: set src attribute for primitives | Eddie Hung | 2020-05-04 | 2 | -2/+6 |
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* / / / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -18/+20 |
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* | | | Merge pull request #1996 from boqwxp/rtlil_source_locations | Eddie Hung | 2020-05-04 | 1 | -13/+13 |
|\ \ \ | |_|/ |/| | | frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`. | ||||
| * | | frontend: Include complete source location instead of just ↵ | Alberto Gonzalez | 2020-05-01 | 1 | -13/+13 |
| | | | | | | | | | | | | `location.first_line` in `frontends/ast/genrtlil.cc`. | ||||
* | | | aiger: fixes for ports that have start_offset != 0 | Eddie Hung | 2020-05-02 | 1 | -30/+47 |
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* | | Merge pull request #2001 from whitequark/wasi | whitequark | 2020-05-01 | 1 | -1/+1 |
|\ \ | | | | | | | Add WASI platform support | ||||
| * | | Add WASI platform support. | whitequark | 2020-04-30 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes the following significant changes: * Patching ezsat and minisat to disable resource limiting code on WASM/WASI, since the POSIX functions they use are unavailable. * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform does not support spawning subprocesses (i.e. Emscripten or WASI). This definition hides the definition of `run_command()`. * Adding a new Makefile flag, DISABLE_SPAWN, present in the same condition. This flag disables all passes that require spawning subprocesses for their function. | ||||
* | | | Merge pull request #1981 from YosysHQ/claire/fix1837 | Claire Wolf | 2020-05-01 | 1 | -0/+4 |
|\ \ \ | |/ / |/| | | Clear current_scope when done with RTLIL generation | ||||
| * | | Clear current_scope when done with RTLIL generation, fixes #1837 | Claire Wolf | 2020-04-22 | 1 | -0/+4 |
| | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | verific: ignore anonymous enums | Eddie Hung | 2020-04-30 | 1 | -1/+4 |
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