| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 |
| |\ | | | | | module->derive() to be lazy and not touch ast if already derived | ||||
| | * | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
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| | * | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
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| * | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 |
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| * | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 2 | -0/+591 |
| |\ | | | | | rpc: new frontend | ||||
| | * | rpc: new frontend. | whitequark | 2019-09-30 | 2 | -0/+591 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design. | ||||
| * | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -2/+6 |
| |\ \ | | | | | | | Open aig frontend as binary file | ||||
| | * | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
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| | * | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 |
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| * / | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵ | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| | | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext | Eddie Hung | 2019-09-18 | 1 | -1/+1 |
| |\ | | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells | ||||
| | * | Revert "parse_xaiger() to do "clean -purge"" | Eddie Hung | 2019-09-04 | 1 | -1/+1 |
| | | | | | | | | | This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5. | ||||
| * | | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix handling of z_digit "?" and fix optimization of cmp with "z" | Clifford Wolf | 2019-09-13 | 1 | -5/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix lexing of integer literals without radix | Clifford Wolf | 2019-09-13 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix lexing of integer literals, fixes #1364 | Clifford Wolf | 2019-09-12 | 2 | -3/+3 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -14/+25 |
| |\ \ | | | | | | | Allow arrival times of sequential outputs to be specified to abc9 | ||||
| | * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-09-04 | 1 | -0/+7 |
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| | * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -0/+5 |
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| | * | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -33/+2 |
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| | * | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -31/+10 |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -1/+4 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 3 | -14/+11 |
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| | * | | | | | | Set abc_flop and use it in toposort | Eddie Hung | 2019-08-19 | 1 | -0/+1 |
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| | * | | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 15 | -124/+172 |
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| | * | | | | | | | Short out async box | Eddie Hung | 2019-07-11 | 1 | -0/+14 |
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| | * | | | | | | | Missing debug message | Eddie Hung | 2019-07-11 | 1 | -0/+1 |
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| | * | | | | | | | Small opt | Eddie Hung | 2019-07-10 | 1 | -2/+1 |
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| | * | | | | | | | Change how to specify flops to ABC again | Eddie Hung | 2019-07-10 | 1 | -10/+6 |
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| | * | | | | | | | Use split_tokens() | Eddie Hung | 2019-07-10 | 1 | -8/+8 |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 3 | -85/+24 |
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| | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-02 | 1 | -0/+2 |
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| | * | | | | | | | | | Refactor and cope with new abc_flop format | Eddie Hung | 2019-07-01 | 1 | -9/+21 |
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| | * | | | | | | | | | Fix spacing | Eddie Hung | 2019-07-01 | 1 | -1/+1 |
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| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-01 | 9 | -77/+189 |
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| | * | | | | | | | | | | Cleanup | Eddie Hung | 2019-06-16 | 1 | -23/+18 |
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| | * | | | | | | | | | | Read init from outputs | Eddie Hung | 2019-06-15 | 1 | -0/+4 |
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| | * | | | | | | | | | | Fix debug message | Eddie Hung | 2019-06-15 | 1 | -0/+1 |
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| | * | | | | | | | | | | Fix log_debug messages | Eddie Hung | 2019-06-15 | 1 | -17/+23 |
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| | * | | | | | | | | | | Missing close bracket | Eddie Hung | 2019-06-15 | 1 | -1/+1 |
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| | * | | | | | | | | | | read_aiger to not require clk_name for latches, plus debug | Eddie Hung | 2019-06-15 | 1 | -21/+37 |
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| * | | | | | | | | | | | Merge pull request #1350 from YosysHQ/clifford/fixsby59 | Clifford Wolf | 2019-09-05 | 1 | -7/+18 |
| |\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" | ||||
| | * | | | | | | | | | | Properly construct $live and $fair cells from "if (...) assume/assert ↵ | Clifford Wolf | 2019-09-02 | 1 | -7/+18 |
| | | |_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/deferred_top | Eddie Hung | 2019-09-03 | 1 | -1/+1 |
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| | * | | | | | | | | | parse_xaiger() to do "clean -purge" | Eddie Hung | 2019-08-29 | 1 | -1/+1 |
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| * | | | | | | | | | Remove newline | Eddie Hung | 2019-08-29 | 1 | -1/+0 |
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| * | | | | | | | | | Restore non-deferred code, deferred case to ignore non constant attr | Eddie Hung | 2019-08-29 | 1 | -5/+12 |
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| * | | | | | | | | | read_verilog -defer should still populate module attributes | Eddie Hung | 2019-08-28 | 1 | -5/+6 |
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