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* Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-302-0/+591
|\ | | | | rpc: new frontend
| * rpc: new frontend.whitequark2019-09-302-0/+591
| | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
* | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-2/+6
|\ \ | | | | | | Open aig frontend as binary file
| * | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
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| * | Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
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* / Force $inout.out ports to begin with '$' to indicate internalEddie Hung2019-09-231-2/+2
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-202-18/+30
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxextEddie Hung2019-09-181-1/+1
|\ | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
| * Revert "parse_xaiger() to do "clean -purge""Eddie Hung2019-09-041-1/+1
| | | | | | | | This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5.
* | Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-14/+25
|\ \ | | | | | | Allow arrival times of sequential outputs to be specified to abc9
| * | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-041-0/+7
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| * | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-0/+5
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| * | | | Remove sequential extensionEddie Hung2019-08-201-33/+2
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| * | | | Use abc_{map,unmap,model}.vEddie Hung2019-08-201-31/+10
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-1/+4
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-193-14/+11
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| * | | | | | Set abc_flop and use it in toposortEddie Hung2019-08-191-0/+1
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| * | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1615-124/+172
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| * | | | | | | Short out async boxEddie Hung2019-07-111-0/+14
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| * | | | | | | Missing debug messageEddie Hung2019-07-111-0/+1
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| * | | | | | | Small optEddie Hung2019-07-101-2/+1
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| * | | | | | | Change how to specify flops to ABC againEddie Hung2019-07-101-10/+6
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| * | | | | | | Use split_tokens()Eddie Hung2019-07-101-8/+8
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-103-85/+24
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| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-021-0/+2
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| * | | | | | | | | Refactor and cope with new abc_flop formatEddie Hung2019-07-011-9/+21
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| * | | | | | | | | Fix spacingEddie Hung2019-07-011-1/+1
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-019-77/+189
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| * | | | | | | | | | CleanupEddie Hung2019-06-161-23/+18
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| * | | | | | | | | | Read init from outputsEddie Hung2019-06-151-0/+4
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| * | | | | | | | | | Fix debug messageEddie Hung2019-06-151-0/+1
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| * | | | | | | | | | Fix log_debug messagesEddie Hung2019-06-151-17/+23
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| * | | | | | | | | | Missing close bracketEddie Hung2019-06-151-1/+1
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| * | | | | | | | | | read_aiger to not require clk_name for latches, plus debugEddie Hung2019-06-151-21/+37
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* | | | | | | | | | | Merge pull request #1350 from YosysHQ/clifford/fixsby59Clifford Wolf2019-09-051-7/+18
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
| * | | | | | | | | | Properly construct $live and $fair cells from "if (...) assume/assert ↵Clifford Wolf2019-09-021-7/+18
| | |_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/deferred_topEddie Hung2019-09-031-1/+1
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| * | | | | | | | | parse_xaiger() to do "clean -purge"Eddie Hung2019-08-291-1/+1
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* | | | | | | | | Remove newlineEddie Hung2019-08-291-1/+0
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* | | | | | | | | Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
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* | | | | | | | | read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
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* | | | | | | | Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
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* | | | | | | | mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
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* | | | | | | Merge pull request #1308 from jakobwenzel/real_paramsClifford Wolf2019-08-201-1/+4
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Handle real values when deriving ast modules
| * | | | | | | handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
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