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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-199-33/+260
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| * Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| * Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| * Add "verific -L"Clifford Wolf2019-10-241-1/+12
| * Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| * Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
| * Fix parsing of .cname BLIF statementsClifford Wolf2019-10-161-1/+1
| * Add .blackbox support to blif front-endClifford Wolf2019-10-161-0/+6
| * Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-145-20/+187
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| | * frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | * sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | * sv: Add %expectDavid Shah2019-10-031-0/+1
| | * sv: Add support for memories of a typedefDavid Shah2019-10-031-6/+20
| | * sv: Add support for memory typedefsDavid Shah2019-10-032-3/+34
| | * sv: Fix typedefs in packagesDavid Shah2019-10-031-4/+10
| | * sv: Fix typedef parametersDavid Shah2019-10-032-6/+48
| | * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-035-11/+89
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-2/+6
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| * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-081-4/+4
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| * | | Fixes for MSVC buildMiodrag Milanovic2019-10-041-2/+6
* | | | Fix merge issuesEddie Hung2019-10-041-1/+1
* | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-4/+4
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| * | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-4/+4
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-033-35/+61
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| * | Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
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| | * Fix for svinterfacesEddie Hung2019-09-301-2/+8
| | * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
| * | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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* | Cleanup $currQ from aigerparseEddie Hung2019-09-301-2/+0
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-303-2/+597
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| * Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-302-0/+591
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| | * rpc: new frontend.whitequark2019-09-302-0/+591
| * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-2/+6
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| | * | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
| | * | Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-2/+2
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| * | Force $inout.out ports to begin with '$' to indicate internalEddie Hung2019-09-231-2/+2
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* | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-6/+13
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-275-35/+73
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| * Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...Clifford Wolf2019-09-202-18/+30
| * Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxextEddie Hung2019-09-181-1/+1
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| | * Revert "parse_xaiger() to do "clean -purge""Eddie Hung2019-09-041-1/+1
| * | Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| * | Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
| * | Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| * | Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
| * | Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-14/+25
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| | * | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-041-0/+7
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