iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	stoi -> atoi	Eddie Hung	2019-08-07	3	-5/+5
*	IdString::str().substr() -> IdString::substr()	Eddie Hung	2019-08-06	1	-1/+1
*	Use std::stoi instead of atoi(<str>.c_str())	Eddie Hung	2019-08-06	3	-5/+5
*	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-06	1	-16/+16
*	Use State::S{0,1}	Eddie Hung	2019-08-06	1	-1/+1
*	Merge pull request #1239 from mmicko/mingw_fix	Clifford Wolf	2019-08-02	1	-0/+4
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\| *	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-01	1	-0/+4
* \|	Merge pull request #1233 from YosysHQ/clifford/defer	Clifford Wolf	2019-07-31	1	-1/+2
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\| *	Call "read_verilog" with -defer from "read"	Clifford Wolf	2019-07-29	1	-1/+2
* \|	verilog_lexer: Increase YY_BUF_SIZE to 65536	David Shah	2019-07-26	1	-0/+3
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*	initialize noblackbox and nowb in AstModule::clone	Jakob Wenzel	2019-07-22	1	-0/+2
*	Fix typo, double "of"	Miodrag Milanovic	2019-07-16	1	-1/+1
*	Fix missing semicolon in Windows-specific code in aigerparse.cc.	William D. Jones	2019-07-14	1	-2/+2
*	genrtlil: emit \src attribute on CaseRule.	whitequark	2019-07-08	1	-0/+1
*	Allow attributes on individual switch cases in RTLIL.	whitequark	2019-07-08	1	-4/+9
*	Merge pull request #1147 from YosysHQ/clifford/fix1144	Clifford Wolf	2019-07-03	1	-81/+14
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\| *	Some cleanups in "ignore specify parser"	Clifford Wolf	2019-07-03	1	-79/+5
\| *	Improve specify dummy parser, fixes #1144	Clifford Wolf	2019-06-28	1	-2/+9
\| *	Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131	Clifford Wolf	2019-06-26	1	-1/+1
* \|	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...	Clifford Wolf	2019-07-02	1	-0/+2
* \|	Replace log_assert() with meaningful log_error()	Eddie Hung	2019-06-28	1	-1/+5
* \|	Refactor for one "abc_carry" attribute on module	Eddie Hung	2019-06-27	1	-31/+37
* \|	Remove unneeded include	Eddie Hung	2019-06-27	1	-3/+0
* \|	Merge origin/master	Eddie Hung	2019-06-27	1	-1/+1
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-24	1	-0/+12
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\| *	Add upto and offset to JSON ports	Miodrag Milanovic	2019-06-21	1	-0/+12
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-21	3	-6/+19
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\| *	Fix typo	Miodrag Milanovic	2019-06-21	1	-1/+1
\| *	Added JSON upto and offset	Clifford Wolf	2019-06-21	1	-0/+12
\| *	Merge pull request #1119 from YosysHQ/eddie/fix1118	Clifford Wolf	2019-06-21	1	-0/+1
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\| \| *	Make genvar a signed type	Eddie Hung	2019-06-20	1	-0/+1
\| * \|	Maintain "is_unsized" state of constants	Eddie Hung	2019-06-20	1	-6/+6
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* \|	Reduce log_debug spam in parse_xaiger()	Eddie Hung	2019-06-21	1	-16/+19
* \|	Workaround issues exposed by gcc-4.8	Eddie Hung	2019-06-21	1	-0/+7
* \|	Fix broken abc9.v test due to inout being 1'bx	Eddie Hung	2019-06-20	1	-3/+10
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-20	6	-15/+77
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\| *	Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...	Clifford Wolf	2019-06-20	1	-1/+7
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\| \| *	Unpacked array declaration using size	Tobias Wölfel	2019-06-19	1	-1/+7
\| * \|	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	5	-9/+44
\| * \|	Add defaultvalue attribute	Clifford Wolf	2019-06-19	1	-0/+11
\| * \|	Fix handling of "logic" variables with initial value	Clifford Wolf	2019-06-19	1	-2/+2
\| * \|	Fixed brojen $error()/$info/$warning() on non-generate blocks	Udi Finkelstein	2019-06-11	2	-3/+13
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* \|	Fix issue with part of PI being 1'bx	Eddie Hung	2019-06-20	1	-4/+6
* \|	Cleanup	Eddie Hung	2019-06-16	1	-20/+1
* \|	Cover __APPLE__ too for little to big endian	Eddie Hung	2019-06-14	1	-4/+7
* \|	Further cleanup based on @daveshah1	Eddie Hung	2019-06-14	1	-10/+20
* \|	Resolve comments from @daveshah1	Eddie Hung	2019-06-14	1	-2/+2
* \|	Cleanup	Eddie Hung	2019-06-14	1	-7/+3
* \|	Add TODO to parse_xaiger	Eddie Hung	2019-06-14	1	-0/+1
* \|	Optimise some more	Eddie Hung	2019-06-13	1	-58/+53