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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-02 11:36:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-07-02 11:36:26 +0200 |
| commit | d206eca03b8aa7bb982fb2486c02c90a61354066 (patch) | |
| tree | 076f2ecb015477a7f6783305ad901f14bf7950eb /frontends | |
| parent | 0067dc44f3928833eede2b9bb40260be78e11a93 (diff) | |
| download | yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.tar.gz yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.tar.bz2 yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.zip | |
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d3fd91473..951d9c66f 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some global state.. its a mess) */ [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { + if (!strcmp(yytext, "default")) + return TOK_DEFAULT; frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_SVA_LABEL; } |