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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:04:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:04:12 -0700 |
| commit | c27ab609faeeb3ae9372ea4cf85e5ac6ba029646 (patch) | |
| tree | 60698848847791dc1f924276c90b5ca2b8cbe7fb /frontends | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-c27ab609faeeb3ae9372ea4cf85e5ac6ba029646.tar.gz yosys-c27ab609faeeb3ae9372ea4cf85e5ac6ba029646.tar.bz2 yosys-c27ab609faeeb3ae9372ea4cf85e5ac6ba029646.zip | |
Make genvar a signed type
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4895d0302..d89b2dc88 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -517,6 +517,7 @@ wire_type_token: TOK_GENVAR { astbuf3->type = AST_GENVAR; astbuf3->is_reg = true; + astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; } | |