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* Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Use C++11 final/override keywords.whitequark2020-06-189-34/+34
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* MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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* MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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* Merge pull request #2131 from YosysHQ/claire/preserveffsclairexen2020-06-101-0/+3
|\ | | | | Do not optimize away FFs in "prep" and Verific front-end
| * Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-0/+3
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | verific - detect missing memory to prevent crash.Miodrag Milanovic2020-06-101-2/+7
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* | Merge pull request #2112 from YosysHQ/claire/fix2040clairexen2020-06-092-0/+58
|\ \ | |/ |/| Add latch detection for use_case_method in part-select write
| * Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-042-0/+58
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Support packed arrays in struct/union.Peter Crozier2020-06-072-17/+136
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* Merge pull request #2041 from PeterCrozier/structclairexen2020-06-046-204/+526
|\ | | | | Implementation of SV structs.
| * Merge branch 'master' into structPeter Crozier2020-06-038-53/+95
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| * | Allow structs within structs.Peter Crozier2020-05-121-7/+18
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| * | Generalise structs and add support for packed unions.Peter Crozier2020-05-126-58/+147
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| * | Implement SV structs.Peter Crozier2020-05-086-205/+427
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* | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-2/+5
|\ \ \ | | | | | | | | abc9: -dff improvements
| * | | aiger: cleanupEddie Hung2020-05-251-2/+5
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* | | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-043-1/+10
|\ \ \ \ | |_|_|/ |/| | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | | frontends/json/jsonparse.cc: Like the upto field read_json can also read the ↵Vamsi K Vytla2020-04-271-1/+6
| | | | | | | | | | | | | | | | signedness of a wire
| * | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-272-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | | Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
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* | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-291-2/+2
|\ \ \ \ | | | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-051-2/+2
| | | | | | | | | | | | | | | | | | | | Fixes #2020.
* | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erangewhitequark2020-05-291-1/+3
|\ \ \ \ \ | | | | | | | | | | | | ilang_lexer: fix check for out of range literal
| * | | | | ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Commit ca70a104 did not use a correct check.
* | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
|\ \ \ \ \ \ | |/ / / / / |/| | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| * | | | | verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
* | | | | | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
* | | | | | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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* | | | | | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
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* | | | | | verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
* | | | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
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* | | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
|\ \ \ \ \ | | | | | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| * | | | | Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | | | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * | | | | verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
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* | | | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
| | | | | | | | | | | | | | | | | | | | Fixes #2058.
* | | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dffEddie Hung2020-05-182-4/+12
|\ \ \ \ \ | | | | | | | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
| * | | | | aiger: -xaiger to return $_FF_ flopsEddie Hung2020-05-141-15/+2
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| * | | | | aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-141-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | Since abc9 doesn't like negative mergeability values
| * | | | | aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
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| * | | | | aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | according to mergeability class, and init state as cell attr
* | | | | | Revert "Add support for non-power-of-two mem chunks in verific importer"Claire Wolf2020-05-171-12/+2
|/ / / / / | | | | | | | | | | | | | | | This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.
* | | | | Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-141-1/+13
|\ \ \ \ \ | | | | | | | | | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * | | | | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | otherwise error
| * | | | | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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* | | | | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
|\ \ \ \ \ | | | | | | | | | | | | Add support for non-power-of-two mem chunks in verific importer
| * | | | | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
| |/ / / / | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
|\ \ \ \ \ | |/ / / / |/| | | | ast: swap range regardless of range_left >= 0
| * | | | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
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* | | | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
|\ \ \ \ \ | | | | | | | | | | | | Avoid switch fall-through warnings
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