Merge branch 'master' into struct

8 files changed, 95 insertions, 53 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6fda92d73..d25587e48 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -454,6 +454,14 @@ void AigerReader::parse_xaiger()
 			for (unsigned i = 0; i < flopNum; i++)
 				mergeability.emplace_back(parse_xaiger_literal(f));
 		}
+		else if (c == 's') {
+			uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			flopNum = parse_xaiger_literal(f);
+			log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+			initial_state.reserve(flopNum);
+			for (unsigned i = 0; i < flopNum; i++)
+				initial_state.emplace_back(parse_xaiger_literal(f));
+		}
 		else if (c == 'n') {
 			parse_xaiger_literal(f);
 			f >> s;
@@ -767,6 +775,7 @@ void AigerReader::post_process()
 		}
 	}
 
+	dict<int, Wire*> mergeability_to_clock;
 	for (uint32_t i = 0; i < flopNum; i++) {
 		RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
 		log_assert(d);
@@ -778,10 +787,9 @@ void AigerReader::post_process()
 		log_assert(q->port_input);
 		q->port_input = false;
 
-		auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
-		ff->setPort(ID::D, d);
-		ff->setPort(ID::Q, q);
+		Cell* ff = module->addFfGate(NEW_ID, d, q);
 		ff->attributes[ID::abc9_mergeability] = mergeability[i];
+		q->attributes[ID::init] = initial_state[i];
 	}
 
 	dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 46ac81212..251a24977 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -45,7 +45,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> outputs;
     std::vector<RTLIL::Wire*> bad_properties;
     std::vector<RTLIL::Cell*> boxes;
-    std::vector<int> mergeability;
+    std::vector<int> mergeability, initial_state;
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
     void parse_aiger();
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 83f34c9e1..fa16b2f2f 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1057,7 +1057,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (!range_valid)
 				log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
 
-			if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
+			if (!(range_left + 1 >= range_right))
 				log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
 
 			RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e8ac4b2f2..e88331621 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1256,7 +1256,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		}
 		if (old_range_valid != range_valid)
 			did_something = true;
-		if (range_valid && range_left >= 0 && range_right > range_left) {
+		if (range_valid && range_right > range_left) {
 			int tmp = range_right;
 			range_right = range_left;
 			range_left = tmp;
@@ -1274,6 +1274,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				range_swapped = children[0]->range_swapped;
 				range_left = children[0]->range_left;
 				range_right = children[0]->range_right;
+				bool force_upto = false, force_downto = false;
+				if (attributes.count(ID::force_upto)) {
+					AstNode *val = attributes[ID::force_upto];
+					if (val->type != AST_CONSTANT)
+						log_file_error(filename, location.first_line, "Attribute `force_upto' with non-constant value!\n");
+					force_upto = val->asAttrConst().as_bool();
+				}
+				if (attributes.count(ID::force_downto)) {
+					AstNode *val = attributes[ID::force_downto];
+					if (val->type != AST_CONSTANT)
+						log_file_error(filename, location.first_line, "Attribute `force_downto' with non-constant value!\n");
+					force_downto = val->asAttrConst().as_bool();
+				}
+				if (force_upto && force_downto)
+					log_file_error(filename, location.first_line, "Attributes `force_downto' and `force_upto' cannot be both set!\n");
+				if ((force_upto && !range_swapped) || (force_downto && range_swapped)) {
+					std::swap(range_left, range_right);
+					range_swapped = force_upto;
+				}
 			}
 		} else {
 			if (!range_valid)
@@ -3719,8 +3738,8 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 		}
 	}
 
-	// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
-	if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
+	// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
+	if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
 		mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
 
 	if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index 62f53d18e..3362ed641 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -91,8 +91,10 @@ USING_YOSYS_NAMESPACE
 [0-9]+'[01xzm-]*	{ rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; }
 -?[0-9]+		{
 	char *end = nullptr;
+	errno = 0;
 	long value = strtol(yytext, &end, 10);
-	if (end != yytext + strlen(yytext))
+	log_assert(end == yytext + strlen(yytext));
+	if (errno == ERANGE)
 		return TOK_INVALID; // literal out of range of long
 	if (value < INT_MIN || value > INT_MAX)
 		return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms)
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index fe4bda68e..cb0368fd5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -974,6 +974,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			module->memories[memory->name] = memory;
 
 			int number_of_bits = net->Size();
+			number_of_bits = 1 << ceil_log2(number_of_bits);
 			int bits_in_word = number_of_bits;
 			FOREACH_PORTREF_OF_NET(net, si, pr) {
 				if (pr->GetInst()->Type() == OPER_READ_PORT) {
@@ -1265,9 +1266,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			int numchunks = int(inst->OutputSize()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
 
-			if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0)
-				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
-
 			for (int i = 0; i < numchunks; i++)
 			{
 				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
@@ -1295,9 +1293,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			int numchunks = int(inst->Input2Size()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
 
-			if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0)
-				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
-
 			for (int i = 0; i < numchunks; i++)
 			{
 				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 6217b5728..e6fa6361e 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -48,16 +48,18 @@ USING_YOSYS_NAMESPACE
 using namespace AST;
 using namespace VERILOG_FRONTEND;
 
+#define YYSTYPE FRONTEND_VERILOG_YYSTYPE
+#define YYLTYPE FRONTEND_VERILOG_YYLTYPE
+
 YOSYS_NAMESPACE_BEGIN
 namespace VERILOG_FRONTEND {
 	std::vector<std::string> fn_stack;
 	std::vector<int> ln_stack;
+	YYLTYPE real_location;
+	YYLTYPE old_location;
 }
 YOSYS_NAMESPACE_END
 
-#define YYSTYPE FRONTEND_VERILOG_YYSTYPE
-#define YYLTYPE FRONTEND_VERILOG_YYLTYPE
-
 #define SV_KEYWORD(_tok) \
 	if (sv_mode) return _tok; \
 	log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
@@ -73,9 +75,6 @@ YOSYS_NAMESPACE_END
 #define YY_INPUT(buf,result,max_size) \
 	result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
 
-YYLTYPE real_location;
-YYLTYPE old_location;
-
 #define YY_USER_ACTION \
        old_location = real_location; \
        real_location.first_line = real_location.last_line; \
@@ -128,7 +127,9 @@ static bool isUserType(std::string &s)
 %x BASED_CONST
 
 %%
-	int comment_caller;
+	// Initialise comment_caller to something to avoid a "maybe undefined"
+	// warning from GCC.
+	int comment_caller = INITIAL;
 
 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
 	fn_stack.push_back(current_filename);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e72d09524..c4867356c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -886,7 +886,19 @@ task_func_port:
 		albuf = $1;
 		astbuf1 = $2;
 		astbuf2 = checkRange(astbuf1, $3);
-	} wire_name | wire_name;
+	} wire_name |
+	{
+		if (!astbuf1) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("task/function argument direction missing");
+			albuf = new dict<IdString, AstNode*>;
+			astbuf1 = new AstNode(AST_WIRE);
+			current_wire_rand = false;
+			current_wire_const = false;
+			astbuf1->is_input = true;
+			astbuf2 = NULL;
+		}
+	} wire_name;
 
 task_func_body:
 	task_func_body behavioral_stmt |
@@ -2299,49 +2311,56 @@ assert_property:
 	};
 
 simple_behavioral_stmt:
-	lvalue '=' delay expr {
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
+	attr lvalue '=' delay expr {
+		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
 		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @1, @4);
+		SET_AST_NODE_LOC(node, @2, @5);
+		append_attr(node, $1);
 	} |
-	lvalue TOK_INCREMENT {
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
+	attr lvalue TOK_INCREMENT {
+		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
 		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @1, @2);
+		SET_AST_NODE_LOC(node, @2, @3);
+		append_attr(node, $1);
 	} |
-	lvalue TOK_DECREMENT {
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
+	attr lvalue TOK_DECREMENT {
+		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
 		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @1, @2);
+		SET_AST_NODE_LOC(node, @2, @3);
+		append_attr(node, $1);
 	} |
-	lvalue OP_LE delay expr {
-		AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
+	attr lvalue OP_LE delay expr {
+		AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
 		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @1, @4);
+		SET_AST_NODE_LOC(node, @2, @5);
+		append_attr(node, $1);
 	};
 
 // this production creates the obligatory if-else shift/reduce conflict
 behavioral_stmt:
 	defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
 	non_opt_delay behavioral_stmt |
-	simple_behavioral_stmt ';' | ';' |
-	hierarchical_id attr {
+	simple_behavioral_stmt ';' |
+	attr ';' {
+		free_attr($1);
+	} |
+	attr hierarchical_id {
 		AstNode *node = new AstNode(AST_TCALL);
-		node->str = *$1;
-		delete $1;
+		node->str = *$2;
+		delete $2;
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-		append_attr(node, $2);
+		append_attr(node, $1);
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
-	TOK_MSG_TASKS attr {
+	attr TOK_MSG_TASKS {
 		AstNode *node = new AstNode(AST_TCALL);
-		node->str = *$1;
-		delete $1;
+		node->str = *$2;
+		delete $2;
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-		append_attr(node, $2);
+		append_attr(node, $1);
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
@@ -2438,8 +2457,6 @@ behavioral_stmt:
 		ast_stack.pop_back();
 	};
 
-	;
-
 unique_case_attr:
 	/* empty */ {
 		$$ = false;
@@ -2534,7 +2551,7 @@ gen_case_item:
 	} case_select {
 		case_type_stack.push_back(0);
 		SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
-	} gen_stmt_or_null {
+	} gen_stmt_block {
 		case_type_stack.pop_back();
 		ast_stack.pop_back();
 	};
@@ -2626,7 +2643,10 @@ module_gen_body:
 	/* empty */;
 
 gen_stmt_or_module_body_stmt:
-	gen_stmt | module_body_stmt;
+	gen_stmt | module_body_stmt |
+	attr ';' {
+		free_attr($1);
+	};
 
 // this production creates the obligatory if-else shift/reduce conflict
 gen_stmt:
@@ -2648,7 +2668,7 @@ gen_stmt:
 		AstNode *block = new AstNode(AST_GENBLOCK);
 		ast_stack.back()->children.push_back(block);
 		ast_stack.push_back(block);
-	} gen_stmt_or_null {
+	} gen_stmt_block {
 		ast_stack.pop_back();
 	} opt_gen_else {
 		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
@@ -2698,11 +2718,8 @@ gen_stmt_block:
 		ast_stack.pop_back();
 	};
 
-gen_stmt_or_null:
-	gen_stmt_block | ';';
-
 opt_gen_else:
-	TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
+	TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
 
 expr:
 	basic_expr {