| Commit message (Expand) | Author | Age | Files | Lines |
* | Merge pull request #1551 from whitequark/manual-cell-operands | Clifford Wolf | 2019-12-05 | 1 | -5/+5 |
|\ |
|
| * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 |
* | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 |
|/ |
|
* | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 |
* | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 |
* | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 |
* | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 |
* | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 |
* | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 |
* | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 |
* | Improve naming scheme for (VHDL) modules imported from Verific | Clifford Wolf | 2019-10-24 | 1 | -3/+26 |
* | Add "verific -L" | Clifford Wolf | 2019-10-24 | 1 | -1/+12 |
* | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
* | Fix handling of "restrict" in Verific front-end | Clifford Wolf | 2019-10-21 | 1 | -1/+1 |
* | Fix parsing of .cname BLIF statements | Clifford Wolf | 2019-10-16 | 1 | -1/+1 |
* | Add .blackbox support to blif front-end | Clifford Wolf | 2019-10-16 | 1 | -0/+6 |
* | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 5 | -20/+187 |
|\ |
|
| * | frontends/ast: code style | David Shah | 2019-10-03 | 1 | -2/+1 |
| * | sv: Fix typedefs in blocks | David Shah | 2019-10-03 | 1 | -2/+2 |
| * | sv: Disambiguate interface ports | David Shah | 2019-10-03 | 1 | -3/+19 |
| * | sv: Fix memories of typedefs | David Shah | 2019-10-03 | 1 | -1/+1 |
| * | sv: Add %expect | David Shah | 2019-10-03 | 1 | -0/+1 |
| * | sv: Add support for memories of a typedef | David Shah | 2019-10-03 | 1 | -6/+20 |
| * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 2 | -3/+34 |
| * | sv: Fix typedefs in packages | David Shah | 2019-10-03 | 1 | -4/+10 |
| * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 2 | -6/+48 |
| * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 5 | -11/+89 |
* | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -4/+4 |
|\ \ |
|
| * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -4/+4 |
* | | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 1 | -2/+6 |
|/ / |
|
* | | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 |
|\ \
| |/
|/| |
|
| * | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
| * | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
* | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 |
|/ |
|
* | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 2 | -0/+591 |
|\ |
|
| * | rpc: new frontend. | whitequark | 2019-09-30 | 2 | -0/+591 |
* | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -2/+6 |
|\ \ |
|
| * | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
| * | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 |
| |/ |
|
* / | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
|/ |
|
* | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #... | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
* | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext | Eddie Hung | 2019-09-18 | 1 | -1/+1 |
|\ |
|
| * | Revert "parse_xaiger() to do "clean -purge"" | Eddie Hung | 2019-09-04 | 1 | -1/+1 |
* | | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
* | | Fix handling of z_digit "?" and fix optimization of cmp with "z" | Clifford Wolf | 2019-09-13 | 1 | -5/+1 |
* | | Fix lexing of integer literals without radix | Clifford Wolf | 2019-09-13 | 1 | -1/+1 |
* | | Fix lexing of integer literals, fixes #1364 | Clifford Wolf | 2019-09-12 | 2 | -3/+3 |
* | | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -14/+25 |
|\ \ |
|
| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-09-04 | 1 | -0/+7 |
| |\| |
|
| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
| |\ \ |
|