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author | Clifford Wolf <clifford@clifford.at> | 2019-12-05 08:24:24 -0800 |
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committer | GitHub <noreply@github.com> | 2019-12-05 08:24:24 -0800 |
commit | 7dece7955e9682dddec67eb99d4f99742e637a07 (patch) | |
tree | 79edd5c9a3f5846d1da74859cea8d1e037b5366c /frontends | |
parent | fcce94010f3282e7f7d3f602b3e710cb7ce524ee (diff) | |
parent | e97e33d00df9d702643a82152aa1becc611ef823 (diff) | |
download | yosys-7dece7955e9682dddec67eb99d4f99742e637a07.tar.gz yosys-7dece7955e9682dddec67eb99d4f99742e637a07.tar.bz2 yosys-7dece7955e9682dddec67eb99d4f99742e637a07.zip |
Merge pull request #1551 from whitequark/manual-cell-operands
Clarify semantics of comb cells, in particular shifts
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/verilog/verilog_parser.y | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index daea3b43a..a30935e0a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2242,7 +2242,7 @@ gen_stmt: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); } opt_arg_list ';'{ - ast_stack.pop_back(); + ast_stack.pop_back(); }; gen_stmt_block: @@ -2413,19 +2413,19 @@ basic_expr: append_attr($$, $2); } | basic_expr OP_SHL attr basic_expr { - $$ = new AstNode(AST_SHIFT_LEFT, $1, $4); + $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4)); append_attr($$, $3); } | basic_expr OP_SHR attr basic_expr { - $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4); + $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4)); append_attr($$, $3); } | basic_expr OP_SSHL attr basic_expr { - $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4); + $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4)); append_attr($$, $3); } | basic_expr OP_SSHR attr basic_expr { - $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4); + $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4)); append_attr($$, $3); } | basic_expr '<' attr basic_expr { |