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* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-022-93/+110
|\ | | | | ast: Add support for $sformatf system function
| * ast: Add support for $sformatf system functionDavid Shah2020-01-192-93/+110
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
|\ \ | | | | | | Add Verific support for OPER_REDUCE_NAND
| * | Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
|\ \ \ | | | | | | | | `verific` pass to print help message when command syntax error
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-2711-229/+347
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| * | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
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| * | | OopsEddie Hung2019-11-191-1/+1
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| * | | Print help message for verific passEddie Hung2019-11-191-9/+12
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* | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
|\ \ \ \ | |_|_|/ |/| | | verific: unflatten struct ports
| * | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
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| * | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* | | Add and use SigSpec::reverse()Eddie Hung2020-01-281-3/+3
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* | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-2/+4
| | | | | | | | | | | | Now done in read_aiger
* | | read_aiger: set abc9_box_seq attrEddie Hung2020-01-241-0/+1
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* | | read_aiger: also parse abc9_mergeabilityEddie Hung2020-01-222-2/+6
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* | | read_aiger: discard LUT inputs with nodeID == 0; not < 2Eddie Hung2020-01-211-1/+1
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* | | read_aiger: ignore constant inputs on LUTsEddie Hung2020-01-211-3/+7
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-2/+2
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| * | read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-142-13/+17
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| * | read_aiger: also rename "$0"Eddie Hung2020-01-141-2/+2
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| * | read_aiger: uniquify wires with $aiger<autoidx> prefixEddie Hung2020-01-132-9/+13
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| * | read_aiger: make $and/$not/$lut the prefix not suffixEddie Hung2020-01-131-5/+5
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* | | abc9: break SCC by setting (* keep *) on output wiresEddie Hung2020-01-131-1/+3
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* | | read_aiger: more accurate debug messageEddie Hung2020-01-091-2/+4
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* | | read_aiger: do not double-count outputs for flopsEddie Hung2020-01-091-6/+0
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-071-5/+20
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| * | read_aiger: consistency between ascii and binary; also name latchesEddie Hung2020-01-071-3/+9
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| * | read_aiger: connect identical signals togetherEddie Hung2020-01-071-0/+1
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| * | read_aiger: cope with latches and POs with same nameEddie Hung2020-01-071-2/+12
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| * | read_aiger: default -clk_name to be emptyEddie Hung2020-01-071-1/+1
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* | | read_aiger fixesEddie Hung2020-01-071-5/+5
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* | | read_aiger: do not process box connections, work standaloneEddie Hung2020-01-071-115/+46
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* | | read_aiger: consistency between ascii and binaryEddie Hung2020-01-071-13/+7
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* | | read_aiger: add -xaiger optionEddie Hung2020-01-061-7/+17
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* | parse_xaiger to not take box_lookupEddie Hung2019-12-312-18/+20
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* | parse_xaiger to reorder ports tooEddie Hung2019-12-311-41/+26
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-0/+16
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| * \ Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-191-0/+16
| |\ \ | | | | | | | | verilog: preserve size of $genval$-s in for loops
| | * | Stray log_dumpEddie Hung2019-12-111-1/+0
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| | * | Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-194-7/+28
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| * | | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-132-2/+2
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* | | aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
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* | | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-171-23/+4
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