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* Merge remote-tracking branch 'origin/master' into eddie/deferred_topEddie Hung2019-09-031-1/+1
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| * parse_xaiger() to do "clean -purge"Eddie Hung2019-08-291-1/+1
* | Remove newlineEddie Hung2019-08-291-1/+0
* | Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
* | read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
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* Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
* mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
* Merge pull request #1308 from jakobwenzel/real_paramsClifford Wolf2019-08-201-1/+4
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| * handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
* | Fix typoEddie Hung2019-08-191-1/+1
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* Merge branch 'master' into eddie/pr1266_againwhitequark2019-08-184-15/+12
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| * Merge pull request #1283 from YosysHQ/clifford/fix1255Clifford Wolf2019-08-172-13/+10
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| | * Fix erroneous ifndef-NDEBUG in verific.ccClifford Wolf2019-08-171-3/+1
| | * Remove unused variableEddie Hung2019-08-161-5/+0
| | * Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-132-9/+13
| * | Change signature of parse_blif to take IdStringEddie Hung2019-08-152-2/+2
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* / Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-121-1/+1
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* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-1/+1
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-108-49/+49
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| * substr() -> compare()Eddie Hung2019-08-075-12/+12
| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-072-19/+19
| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-38/+36
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| * | stoi -> atoiEddie Hung2019-08-073-5/+5
| * | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
| * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-063-5/+5
| * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-16/+16
| * | Use State::S{0,1}Eddie Hung2019-08-061-1/+1
* | | Merge pull request #1261 from YosysHQ/clifford/verific_initClifford Wolf2019-08-102-7/+60
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| * | | Automatically prune init attributes in verific front-end, fixes #1237Clifford Wolf2019-08-072-7/+60
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* | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithroEddie Hung2019-08-091-0/+1
* | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-1/+1
* | | Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
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* | Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
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| * | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
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* | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-23/+34
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| * Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
* | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-021-0/+4
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| * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-0/+4
* | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-311-1/+2
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| * Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
* | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
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* initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
* Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
* Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-4/+9
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
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| * Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| * Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| * Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1